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參數(shù)資料
| 型號(hào)： | PLUS405-55N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | PLD |
| 英文描述： | Programmable logic sequencer 16 】 64 】 8 |
| 中文描述： | OT PLD, 8 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 327K |
| 代理商： | PLUS405-55N |
Philips Semiconductors
Product specification
PLUS405-37/-45
Programmable logic sequencers
(16
×
64
×
8)
1996 Nov 12
15
“OR” ARRAY – J-K FUNCTION – (N), (F)
CODE
H
ACTION
CODE
L
ACTION
RESET
SET
N, F
N, F
T
n
J
Q
K
CODE
O
ACTION
TOGGLE
1, 6
N, F
N, F
T
n
J
Q
K
N, F
N, F
T
n
J
Q
K
N, F
N, F
T
n
J
Q
K
CODE
–
ACTION
NO CHANGE
SP00268
“COMPLEMENT” ARRAY – (C)
CODE
O
ACTION
INACTIVE
1, 3
CODE
ACTION
CODE
ACTION
CODE
ACTION
GENERATE
A
PROPAGATE
TRANSPARENT
–
T
n
c
c
T
n
c
T
n
c
T
n
c
c
c
c
SP00269
CLOCK OPTION – (CLK1/CLK2)
OPTION
CLK1 ONLY
1
CODE
L
CLK2
CLK1
OPTION
CODE
H
CLK1 and CLK2
5
CLK2
CLK1
SP00270
NOTES:
1. This is the initial unprogrammed state of all links.
2. Any gate T
n
will be unconditionally inhibited if any one of its I or P link pairs is left intact.
3. To prevent oscillations, this state is not allowed for C link pairs coupled to active gates T
n
.
4. These states are not allowed when using INITIALIZATION option.
5. Input buffer I5 must be deleted from the AND array (i.e., all fuse locations “Don’t Care”) when using second clock option.
6. A single product term cannot drive more than 8 registers by itself when used in TOGGLE mode.
PROGRAMMING/SOFTWARE SUPPORT
Refer to Section 9
(Development Software)
and Section 10
(Third-party Programmer/ Software Support)
of this data handbook
for additional information.
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