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參數(shù)資料
| 型號： | PLL1708DBQR |
| 英文描述： | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| 中文描述： | 3.3 V雙鎖相環(huán)MULTICLOCK發(fā)生器 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大?。?/td> | 171K |
| 代理商： | PLL1708DBQR |
SLES065
–
DECEMBER 2002
www.ti.com
3
ELECTRICAL CHARACTERISTICS
all specifications at TA = 25
°
C, VDD1
–
VDD3 (= VDD) = VCC = 3.3 V, fM = 27 MHz, crystal oscillation, fS = 48 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DIGITAL INPUT/OUTPUT
Logic input
VIH (1)
VIL (1)
IIH (1)
IIL (1)
VIN = 0 V
Logic output
VOH (2)
VOL (2)
IOL = 4 mA
Standard fS
Double fS
Sampling frequency
Half fS
Sam ling frequency
Standard fS
PLL1708
Double fS
MASTER CLOCK (MCKO1, MCKO2) CHARACTERISTICS
(fM = 27 MHz, C1 = C2 = 15 pF, CL = 20 pF on measurement pin)
Master clock frequency
VIH
VIL
IIH
IIL
VIN = 0 V
Output voltage (4)
Output rise time
20% to 80% of VDD
Output fall time
80% to 20% of VDD
For crystal oscillation
For external clock
Clock jitter (5)
Power-up time (6)
PLL AC CHARACTERISTICS (SCKO0
–
SCKO3)
(fM = 27 MHz, CL = 20 pF on measurement pin)
SCKO0
Fixed
SCKO1
SCKO2
256 fS
SCKO3
Output system clock
384 fS
SCKO0
frequency
Fixed
SCKO1
SCKO2
256 fS
SCKO3
384 fS
Output rise time
20% to 80% of VDD
Output fall time
80% to 20% of VDD
Output duty cycle
(1)Pins 5, 6, 7, 12: FS1/MD, FS2/MC, SR/MS, CSEL (Schmitt-trigger input with internal pulldown, 3.3-V tolerant)
(2)Pins 2, 3, 14, 15, 18, 19: SCKO2, SCKO3, MCKO1, MCKO2, SCKO0, SCKO1
(3)Pin 10: XT1
(4)Pin 11: XT2
(5)Jitter performance is specified as standard deviation of jitter for 27-MHz crystal oscillation and default SCKO frequency setting. Jitter
performance varies with master clock mode, SCKO frequency setting and load capacitance on each clock output.
(6)The delay time from power on to oscillation
(7)The settling time when the sampling frequency is changed
(8)The delay time from power on to lockup
(9)fM = 27-MHz crystal oscillation, no load on MCKO1, MCKO2, SCKO0, SCKO1, SCKO2, SCKO3. Power supply current varies with sampling
frequency selection and load condition.
(10)While all bits of CE[6:1] are 0, the PLL1708 goes into power-down mode.
MIN
TYP
MAX
UNIT
CMOS compatible
0.7VDD
3.6
Vdc
Input logic level
0.3 VDD
VIN = VDD
65
100
±
10
μ
A
Input logic current
CMOS
VDD
–
0.4 V
IOH =
–
4 mA
Vdc
Vdc
Output logic level
0.4
48
96
24
48
96
PLL1707
32
64
16
32
64
44.1
88.2
22.05
44.1
88.2
kHz
26.73
27
27.27
MHz
0.7 VCC
V
Input level(3)
0.3 VCC
VIN = VCC
±
10
±
10
μ
A
Input current(3)
3.5
2.0
2.0
51%
50%
50
0.5
Vp-p
ns
ns
Duty cycle
45%
55%
ps
ms
1.5
33.8688
Selectable for 48 kHz
24.576
8.192
12.288
36.864
24.576
36.864
PLL1707
12.288
18.432
33.8688
24.576
12.288
18.432
MHz
Out ut system clock
Selectable for 48 kHz
12.288
4.096
6.144
36.864
24.576
36.864
PLL1708
2.0
2.0
50
ns
ns
%
45
55
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PDF描述 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1708DBQRG4 | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Dual PLL Multi Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1720A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHASE LOCKED LOOP |
| PLL-17-Y2-1 | 功能描述:電線鑒定 Laser, Comp Label, Polyester, 1.88" W x RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| PLL-17-Y2-2.5 | 功能描述:電線鑒定 Laser, Comp Label, Polyester, 1.88" W x RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長度:1 in |
| PLL-17-Y2Y-1 | 制造商:Panduit Corp 功能描述: |
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