- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382394 > PLL1708DBQR 3.3 V DUAL PLL MULTICLOCK GENERATOR PDF資料下載
參數(shù)資料
| 型號(hào)： | PLL1708DBQR |
| 英文描述： | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| 中文描述： | 3.3 V雙鎖相環(huán)MULTICLOCK發(fā)生器 |
| 文件頁數(shù)： | 11/22頁 |
| 文件大小： | 171K |
| 代理商： | PLL1708DBQR |
SLES065
–
DECEMBER 2002
www.ti.com
11
Table 2. Sampling Frequencies
SAMPLING RATE
Half sampling frequencies
Standard sampling frequencies
Double sampling frequencies
PLL1708 only
SAMPLING FREQUENCY (kHz)
16
22.05
32
44.1
64
88.2
24
48
96
Table 3. Sampling Frequencies and System Clock Output Frequencies
SAMPLING FREQUENCY (kHz)
SAMPLING RATE
256 fS
SCKO2 (MHZ)
4.096
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
384 fS
SCKO3 (MHZ)
6.144
8.4672
9.216
12.288
16.9344
18.432
24.576
33.8688
36.864
16
22.05
24
32
44.1
48
64
88.2
96
Half
Half
Half
Standard
Standard
Standard
Double
Double
Double
PLL1708 only
Response time from power on (or applying the clock to XT1) to SCKO settling time is typically 3 ms. Delay time from
sampling frequency change to SCKO settling is 300 ns maximum. Figure 10 illustrates SCKO transient timing in the
PLL1708.
SCKO0
SCKO1
300 ns
SCKO2
SCKO3
MS
Stable
Clock Transition Region
Stable
33.8688 , 36.864, or 24.576 MHz
1
–
2 Clocks of MCKO1, 2
Figure 10. System Clock Transient Timing
The delay time for hardware control to use SR, FS2, FS1, or CSEL is 150 ns maximum. Figure 11 illustrates SCKO transient
timing in the PLL1707. Clock transient timing is not synchronized with the SCKOs. External buffers are recommended on
all output clocks in order to avoid degrading the jitter performance of the PLL1707/8.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL1707 | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLL1708 | 3.3 V DUAL PLL MULTICLOCK GENERATOR |
| PLS100 | Programmable logic arrays 16 】 48 】 8 |
| PLS101 | Programmable logic arrays 16 】 48 】 8 |
| PLS101A | Programmable logic arrays 16 】 48 】 8 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLL1708DBQRG4 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 Dual PLL Multi Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| PLL1720A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PHASE LOCKED LOOP |
| PLL-17-Y2-1 | 功能描述:電線鑒定 Laser, Comp Label, Polyester, 1.88" W x RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PLL-17-Y2-2.5 | 功能描述:電線鑒定 Laser, Comp Label, Polyester, 1.88" W x RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PLL-17-Y2Y-1 | 制造商:Panduit Corp 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。