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- 您現(xiàn)在的位置:買賣IC網(wǎng) > PDF目錄3877 > PIC18F4515-E/PT (Microchip Technology)IC MCU FLASH 24KX16 44TQFP PDF資料下載
參數(shù)資料
型號(hào):
PIC18F4515-E/PT
廠商:
Microchip Technology
文件頁(yè)數(shù):
163/234頁(yè)
文件大小:
0K
描述:
IC MCU FLASH 24KX16 44TQFP
標(biāo)準(zhǔn)包裝:
160
系列:
PIC® 18F
核心處理器:
PIC
芯體尺寸:
8-位
速度:
25MHz
連通性:
I²C,SPI,UART/USART
外圍設(shè)備:
欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù):
36
程序存儲(chǔ)器容量:
48KB(24K x 16)
程序存儲(chǔ)器類型:
閃存
RAM 容量:
3.8K x 8
電壓 - 電源 (Vcc/Vdd):
4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器:
A/D 13x10b
振蕩器型:
內(nèi)部
工作溫度:
-40°C ~ 125°C
封裝/外殼:
44-TQFP
包裝:
托盤
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PIC18F2X1X/4X1XDS39636D-page 36 2009 Microchip Technology Inc.3.1.3CLOCK TRANSITIONS ANDSTATUS INDICATORSThe length of the transition between clock sources isthe sum of two cycles of the old clock source and threeto four cycles of the new clock source. This formulaassumes that the new clock source is stable.Three bits indicate the current clock source and itsstatus. They are: OSTS (OSCCON<3>) IOFS (OSCCON<2>) T1RUN (T1CON<6>)In general, only one of these bits will be set while in agiven power-managed mode. When the OSTS bit isset, the primary clock is providing the device clock.When the IOFS bit is set, the INTOSC output isproviding a stable 8 MHz clock source to a divider thatactually drives the device clock. When the T1RUN bit isset, the Timer1 oscillator is providing the clock. If noneof these bits are set, then either the INTRC clocksource is clocking the device, or the INTOSC source isnot yet stable.If the internal oscillator block is configured as theprimary clock source by the FOSC3:FOSC0 Configura-tion bits, then both the OSTS and IOFS bits may be setwhen in PRI_RUN or PRI_IDLE modes. This indicatesthat the primary clock (INTOSC output) is generating astable 8 MHz output. Entering another power-managedRC mode at the same frequency would clear the OSTSbit.3.1.4MULTIPLE SLEEP COMMANDSThe power-managed mode that is invoked with theSLEEP instruction is determined by the setting of theIDLEN bit at the time the instruction is executed. Ifanother SLEEP instruction is executed, the device willenter the power-managed mode specified by IDLEN atthat time. If IDLEN has changed, the device will enterthe new power-managed mode specified by the newsetting.3.2Run ModesIn the Run modes, clocks to both the core andperipherals are active. The difference between thesemodes is the clock source.3.2.1PRI_RUN MODEThe PRI_RUN mode is the normal, full power executionmode of the microcontroller. This is also the defaultmode upon a device Reset, unless Two-Speed Start-upis enabled (see Section 22.3 “Two-Speed Start-up”for details). In this mode, the OSTS bit is set. The IOFSbit may be set if the internal oscillator block is theprimary clock source (see Section 2.7.1 “Oscillator3.2.2SEC_RUN MODEThe SEC_RUN mode is the compatible mode to the“clock switching” feature offered in other PIC18devices. In this mode, the CPU and peripherals areclocked from the Timer1 oscillator. This gives users theoption of lower power consumption while still using ahigh accuracy clock source.SEC_RUN mode is entered by setting the SCS1:SCS0bits to ‘01’. The device clock source is switched to theTimer1 oscillator (see Figure 3-1), the primary oscilla-tor is shut down, the T1RUN bit (T1CON<6>) is set andthe OSTS bit is cleared.On transitions from SEC_RUN mode to PRI_RUN, theperipherals and CPU continue to be clocked from theTimer1 oscillator while the primary clock is started.When the primary clock becomes ready, a clock switchback to the primary clock occurs (see Figure 3-2).When the clock switch is complete, the T1RUN bit iscleared, the OSTS bit is set and the primary clock isproviding the clock. The IDLEN and SCS bits are notaffected by the wake-up; the Timer1 oscillatorcontinues to run.Note 1: Caution should be used when modifying asingle IRCF bit. If VDD is less than 3V, it ispossible to select a higher clock speedthan is supported by the low VDD.Improper device operation may result ifthe VDD/FOSC specifications are violated.2: Executing a SLEEP instruction does notnecessarily place the device into Sleepmode. It acts as the trigger to place thecontroller into either the Sleep mode orone of the Idle modes, depending on thesetting of the IDLEN bit.Note:The Timer1 oscillator should already berunning prior to entering SEC_RUN mode.If the T1OSCEN bit is not set when theSCS1:SCS0 bits are set to ‘01’, entry toSEC_RUN mode will not occur. If theTimer1 oscillator is enabled but not yetrunning, device clocks will be delayed untilthe oscillator has started. In such situa-tions, initial oscillator operation is far fromstable and unpredictable operation mayresult.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC18F4515-I/ML
功能描述:8位微控制器 -MCU 48KB 3968 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F4515-I/P
功能描述:8位微控制器 -MCU 48KB 3968 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F4515-I/PT
功能描述:8位微控制器 -MCU 48KB 3968 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F4515T-I/ML
功能描述:8位微控制器 -MCU 48KB 3968 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F4515T-I/PT
功能描述:8位微控制器 -MCU 48KB 3968 RAM 36I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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