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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F4515-E/PT
寤犲晢锛� Microchip Technology
鏂囦欢闋佹暩(sh霉)锛� 145/234闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC MCU FLASH 24KX16 44TQFP
妯欐簴鍖呰锛� 160
绯诲垪锛� PIC® 18F
鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 25MHz
閫ｉ€氭€э細 I²C锛孲PI锛孶ART/USART
澶栧湇瑷倷锛� 娆犲妾㈡脯/寰╀綅锛孒LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 36
绋嬪簭瀛樺劜鍣ㄥ閲忥細 48KB锛�24K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
RAM 瀹归噺锛� 3.8K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 13x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 44-TQFP
鍖呰锛� 鎵樼洡
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2003 Microchip Technology Inc.
DS39582B-page 227
PIC16F87XA
I2C Master Mode (Reception, 7-bit Address) ........... 103
I2C Master Mode (Transmission,
I2C Slave Mode (Transmission, 10-bit Address) ........ 89
I2C Slave Mode (Transmission, 7-bit Address) .......... 87
I2C Slave Mode with SEN = 1 (Reception,
I2C Slave Mode with SEN = 0 (Reception,
I2C Slave Mode with SEN = 0 (Reception,
I2C Slave Mode with SEN = 1 (Reception,
Parallel Slave Port (PIC16F874A/877A Only) .......... 187
Parallel Slave Port (PSP) Read ................................. 52
Parallel Slave Port (PSP) Write ................................. 52
Reset, Watchdog Timer, Start-up Timer
Slave Mode General Call Address Sequence
(7 or 10-bit Address Mode) ................................ 94
Slow Rise Time (MCLR Tied to VDD via
SPI Master Mode (CKE = 0, SMP = 0) .................... 188
SPI Master Mode (CKE = 1, SMP = 1) .................... 188
SPI Mode (Slave Mode with CKE = 0) ....................... 78
SPI Mode (Slave Mode with CKE = 1) ....................... 78
Stop Condition Receive or Transmit Mode .............. 104
Synchronous Reception
Synchronous Transmission (Through TXEN) .......... 122
Time-out Sequence on Power-up
(MCLR Not Tied to VDD)
Time-out Sequence on Power-up (MCLR Tied
Timer0 and Timer1 External Clock .......................... 185
USART Synchronous Receive
USART Synchronous Transmission
Wake-up from Sleep via Interrupt ............................ 157
U
Address Detect Enable (ADDEN Bit) ....................... 112
Asynchronous Receive (9-bit Mode) ........................ 119
See Asynchronous Receive (9-bit Mode).
Baud Rate Generator (BRG) ................................... 113
Baud Rates, Asynchronous Mode
Baud Rates, Asynchronous Mode
High Baud Rate Select (BRGH Bit) ................. 111
Clock Source Select (CSRC Bit) .............................. 111
Continuous Receive Enable (CREN Bit) .................. 112
Receive Data, 9th Bit (RX9D Bit) ............................. 112
Receive Enable, 9-bit (RX9 Bit) ............................... 112
Serial Port Enable (SPEN Bit) ..........................111, 112
Single Receive Enable (SREN Bit) .......................... 112
Synchronous Master Reception ............................... 123
Synchronous Master Transmission ......................... 121
Synchronous Slave Reception ................................. 125
Synchronous Slave Transmit ................................... 124
Transmit Data, 9th Bit (TX9D) ................................. 111
Transmit Enable (TXEN Bit) .................................... 111
Transmit Enable, 9-bit (TX9 Bit) .............................. 111
Transmit Shift Register Status (TRMT Bit) .............. 111
USART Synchronous Receive Requirements ................. 193
V
Voltage Reference Specifications .................................... 180
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