dsPIC33F
DS70165E-page 132
Preliminary
2007 Microchip Technology Inc.
REGISTER 6-33:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
R-0
R/W-0
U-0
R-0
—
—ILR<3:0>
bit 15
bit 8
U-0
R-0
—
VECNUM<6:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-8
ILR: New CPU Interrupt Priority Level bits
1111
= CPU Interrupt Priority Level is 15
0001
= CPU Interrupt Priority Level is 1
0000
= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM: Vector Number of Pending Interrupt bits
0111111
= Interrupt Vector pending is number 135
0000001
= Interrupt Vector pending is number 9
0000000
= Interrupt Vector pending is number 8
