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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC18F23K20-I/MV |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 136/234闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU 8BIT 8KB FLASH 28UQFN |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 91 |
| 绯诲垪锛� | PIC® XLP™ 18F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 64MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯/寰�(f霉)浣�锛孒LVD锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 24 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 8KB锛�4K x 16锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 512 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.8 V ~ 3.6 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 11x10b |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 28-UFQFN 瑁搁湶鐒婄洡 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 655 (CN2011-ZH PDF) |
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dsPIC33F
DS70165E-page 218
Preliminary
2007 Microchip Technology Inc.
bit 5
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that will be transmitted when the software initiates an Acknowledge sequence.
1
= Send NACK during Acknowledge
0
= Send ACK during Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1
= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0
= Acknowledge sequence not in progress
bit 3
RCEN: Receive Enable bit (when operating as I2C master)
1
= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0
= Receive sequence not in progress
bit 2
PEN: Stop Condition Enable bit (when operating as I2C master)
1
= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0
= Stop condition not in progress
bit 1
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1
= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence.
0
= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1
= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0
= Start condition not in progress
REGISTER 18-1:
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
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