參數(shù)資料
型號: PIC16LF818T-I/SS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封裝: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件頁數(shù): 175/176頁
文件大?。?/td> 3124K
代理商: PIC16LF818T-I/SS
PIC16F818/819
DS39598E-page 96
2004 Microchip Technology Inc.
FIGURE 12-6:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
12.10 Interrupts
The PIC16F818/819 has up to nine sources of inter-
rupt. The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector
immediately. Individual
interrupts
can
be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Register, PIR1. The corresponding
interrupt enable bits are contained in Special Function
Register, PIE1 and the peripheral interrupt enable bit is
contained in Special Function Register, INTCON.
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software
before
re-enabling
interrupts
to
avoid
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs relative to
the current Q cycle. The latency is the same for one or
two-cycle instructions. Individual interrupt flag bits are
set regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
FIGURE 12-7:
INTERRUPT LOGIC
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
0V
1V
5V
TPWRT
TOST
Note:
Individual interrupt
flag bits
are
set
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
ADIF
ADIE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (if in Sleep mode)
Interrupt to CPU
EEIF
EEIE
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