參數(shù)資料
型號: PIC16LF818T-I/SS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封裝: 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件頁數(shù): 137/176頁
文件大小: 3124K
代理商: PIC16LF818T-I/SS
2004 Microchip Technology Inc.
DS39598E-page 61
PIC16F818/819
7.8
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate
a
“special
event
trigger”
signal
(CCP1M3:CCP1M0 = 1011), the signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Timer1 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L
register pair effectively becomes the period register for
Timer1.
7.9
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
TMR1H and TMR1L registers are not reset to 00h on a
POR or any other Reset, except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other Resets, the register
is unaffected.
7.10
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
7.11
Using Timer1 as a
Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
gives users the option to include RTC functionality in
their applications. This is accomplished with an inex-
pensive watch crystal to provide an accurate time base
and several lines of application code to calculate the
time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 7-3, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow, triggers the interrupt and calls
the routine which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflows.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it; the simplest method is to set the MSb of TMR1H
with a BSF instruction. Note that the TMR1L register is
never preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the routine,
RTCinit
. The Timer1 oscillator must also be enabled
and running at all times.
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