參數(shù)資料
型號： PIC16LF818T-I/SS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PDSO20
封裝： 0.209 INCH, PLASTIC, MO-150, SSOP-20
文件頁數(shù)： 165/176頁
文件大?。?/td> 3124K
代理商： PIC16LF818T-I/SS
2003 Microchip Technology Inc.
DS39598D-page 87
PIC16F818/819
11.5
A/D Operation During Sleep
The A/D module can operate during Sleep mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
Sleep. If the A/D interrupt is not enabled, the A/D
module will then be turned off, although the ADON bit
will remain set.
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Turning off the A/D places the A/D module in its lowest
current consumption state.
11.6
Effects of a Reset
A device Reset forces all registers to their Reset state.
The A/D module is disabled and any conversion in
progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is
not
modified
for
a
Power-on
Reset.
The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
11.7
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0
bits
(CCP1CON<3:0>)
be
programmed as ‘1011’ and that the A/D module is
enabled (ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with
minimal
software
overhead
(moving
the
ADRESH:ADRESL to the desired location). The appro-
priate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module but will still reset the Timer1 counter.
TABLE 11-2:
REGISTERS/BITS ASSOCIATED WITH A/D
Note:
For the A/D module to operate in Sleep,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in Sleep, ensure the SLEEP
instruction
immediately
follows
the
instruction that sets the GO/DONE bit.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh,8Bh
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
0Ch
PIR1
—ADIF
—
SSPIF
CCP1IF
TMR2IF TMR1IF
-0-- 0000
8Ch
PIE1
—ADIE
—
SSPIE
CCP1IE
TMR2IE TMR1IE -0-- 0000
-0-- 0000
1Eh
ADRESH
A/D Result Register High Byte
xxxx xxxx
uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0
GO/DONE
—ADON
0000 00-0
9Fh
ADCON1
ADFM
ADCS2
—
PCFG3
PCFG2
PCFG1
PCFG0
00-- 0000
05h
PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxx0 0000
uuu0 0000
85h
TRISA
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
1111 1111
Legend:
x
= unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
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