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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PIC16F87T-E/SS |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 64/200闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 4KX14 EEPROM 20SSOP |
| 妯欐簴鍖呰锛� | 1,600 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | 娆犲妾㈡脯/寰╀綅锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 16 |
| 绋嬪簭瀛樺劜鍣ㄥ閲忥細 | 7KB锛�4K x 14锛� |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | 闁冨瓨 |
| EEPROM 澶�?銆�?/td> | 256 x 8 |
| RAM 瀹归噺锛� | 368 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鎸暕鍣ㄥ瀷锛� | 鍏�(n猫i)閮� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 20-SSOP锛�0.209"锛�5.30mm 瀵級 |
| 鍖呰锛� | 甯跺嵎 (TR) |
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156
8008H鈥揂VR鈥�04/11
ATtiny48/88
15.10 Compatibility with SMBus
As with any other I
2C-compliant interface there are known compatibility issues the designer
should be aware of before connecting a TWI device to SMBus devices. For use in SMBus envi-
ronments, the following should be noted:
All I/O pins of an AVR, including those of the two-wire interface, have protection diodes to
both supply voltage and ground. See Figure 10-1 on page 60. This is in contradiction to the
requirements of the SMBus specifications. As a result, supply voltage mustn鈥檛 be removed
from the AVR or the protection diodes will pull the bus lines down. Power down and sleep
modes is not a problem, provided supply voltages remain.
The data hold time of the TWI is lower than specified for SMBus.
SMBus has a low speed limit, while I
2C hasn鈥檛. As a master in an SMBus environment, the
AVR must make sure bus speed does not drop below specifications, since lower bus speeds
trigger timeouts in SMBus slaves. If the AVR is configured a slave there is a possibility of a
bus lockup, since the TWI module doesn't identify timeouts.
15.11 Register Description
15.11.1
TWBR 鈥� TWI Bit Rate Register
Bits 7:0 鈥� TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See 鈥淏it Rate Generator
Unit鈥� on page 135 for calculating bit rates.
If the TWI operates in Master mode TWBR must be set to 10, or higher.
15.11.2
TWCR 鈥� TWI Control Register
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
Bit 7 鈥� TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
Bit
7
654
32
10
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
TWBR
Read/Write
R/W
Initial Value
0
Bit
7
654
32
10
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
鈥�
TWIE
TWCR
Read/Write
R/W
R
R/W
R
R/W
Initial Value
0
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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| PIC16F87T-I/ML | IC MCU FLASH 4KX14 EEPROM 28QFN |
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鐩搁棞浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| PIC16F87T-I/ML | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 7KB 368 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
| PIC16F87T-I/SO | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 7KB 368 RAM 16 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰ㄦ牸:SMD/SMT |
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