215
8008H–AVR–04/11
ATtiny48/88
22.10 Parallel Programming Characteristics
Figure 22-6. Parallel Programming Timing, Including some General Timing Requirements
Figure 22-7. Parallel Programming Timing, Loading Sequence with Timing Requirement
s Note:
1. The timing requirements shown in Figure 22-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation. Data & Contol
(DATA, XA0/1, BS1, BS2)
CLKI
t
XHXL
t
WLWH
t
DVXH
t
XLDX
t
PLWL
t
WLRH
WR
RDY/BSY
PAGEL
t
PHPL
t
PLBX
t
BVPH
t
XLWL
t
WLBX
t
BVWL
WLRL
CLKI
PAGEL
t
PLXH
XLXH
t
XLPH
z
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
DATA
BS1
XA0
XA1
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD DATA
LOAD ADDRESS
(LOW BYTE)