- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨�(m菐i)璩�(m脿i)IC缍�(w菐ng) > PDF鐩寗3821 > PIC16F877A-I/L (Microchip Technology)IC MCU FLASH 8KX14 EE 44PLCC PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16F877A-I/L |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 61/234闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU FLASH 8KX14 EE 44PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 27 |
| 绯诲垪锛� | PIC® 16F |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 20MHz |
| 閫ｉ€氭€э細 | I²C锛孲PI锛孶ART/USART |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 33 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 14KB锛�8K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ(l猫i)鍨嬶細 | 闁冨瓨 |
| EEPROM 澶у皬锛� | 256 x 8 |
| RAM 瀹归噺锛� | 368 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4 V ~ 5.5 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x10b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 641 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164309-ND - MODULE SKT FOR PM3 44PLCC 444-1001-ND - DEMO BOARD FOR PICMICRO MCU 309-1040-ND - ADAPTER 44-PLCC ZIF TO 40-DIP 309-1039-ND - ADAPTER 44-PLCC TO 40-DIP |
| 鍏跺畠鍚嶇ū(ch膿ng)锛� | PIC16F877AI/L |
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2003 Microchip Technology Inc.
DS39582B-page 151
PIC16F87XA
FIGURE 14-6:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD VIA RC NETWORK)
TRISD
73A
74A
76A
77A
1111 1111
uuuu uuuu
TRISE
73A
74A
76A
77A
0000 -111
uuuu -uuu
PIE1
73A
74A
76A
77A
r000 0000
ruuu uuuu
73A
74A
76A
77A
0000 0000
uuuu uuuu
PIE2
73A
74A
76A
77A
-0-0 0--0
-u-u u--u
PCON
73A
74A
76A
77A
---- --qq
---- --uu
SSPCON2
73A
74A
76A
77A
0000 0000
uuuu uuuu
PR2
73A
74A
76A
77A
1111 1111
SSPADD
73A
74A
76A
77A
0000 0000
uuuu uuuu
SSPSTAT
73A
74A
76A
77A
--00 0000
--uu uuuu
TXSTA
73A
74A
76A
77A
0000 -010
uuuu -uuu
SPBRG
73A
74A
76A
77A
0000 0000
uuuu uuuu
CMCON
73A
974
76A
77A
0000 0111
uuuu uuuu
CVRCON
73A
74A
76A
77A
000- 0000
uuu- uuuu
ADRESL
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
ADCON1
73A
74A
76A
77A
00-- 0000
uu-- uuuu
EEDATA
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
EEADR
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
EEDATH
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
EEADRH
73A
74A
76A
77A
xxxx xxxx
uuuu uuuu
EECON1
73A
74A
76A
77A
x--- x000
u--- u000
u--- uuuu
EECON2
73A
74A
76A
77A
---- ----
TABLE 14-6:
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset
Wake-up via WDT or
Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as 鈥�0鈥�, q = value depends on condition,
r
= reserved, maintain clear. Shaded cells indicate conditions do not apply for the designated device.
Note 1:
One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up).
2:
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3:
See Table 14-5 for Reset value for specific condition.
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
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| PIC16F877AT-E/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 20MHz 8K Flash RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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