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  • 鍙冩暩(sh霉)璩囨枡
    鍨嬭櫉锛� PIC16F877A-I/L
    寤犲晢锛� Microchip Technology
    鏂囦欢闋佹暩(sh霉)锛� 234/234闋�
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    EEPROM 澶�?銆�?/td> 256 x 8
    RAM 瀹归噺锛� 368 x 8
    闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4 V ~ 5.5 V
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    鍏跺畠鍚嶇ū锛� PIC16F877AI/L
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    2003 Microchip Technology Inc.
    DS39582B-page 97
    PIC16F87XA
    9.4.7
    BAUD RATE GENERATOR
    In I2C Master mode, the Baud Rate Generator (BRG)
    reload value is placed in the lower 7 bits of the
    SSPADD register (Figure 9-17). When a write occurs to
    SSPBUF, the Baud Rate Generator will automatically
    begin counting. The BRG counts down to 0 and stops
    until another reload has taken place. The BRG count is
    decremented twice per instruction cycle (TCY) on the
    Q2 and Q4 clocks. In I2C Master mode, the BRG is
    reloaded automatically.
    Once the given operation is complete (i.e., transmis-
    sion of the last data bit is followed by ACK), the internal
    clock will automatically stop counting and the SCL pin
    will remain in its last state.
    demonstrates
    clock
    rates
    based
    on
    instruction cycles and the BRG value loaded into
    SSPADD.
    FIGURE 9-17:
    BAUD RATE GENERATOR BLOCK DIAGRAM
    TABLE 9-3:
    I2C CLOCK RATE W/BRG
    SSPM3:SSPM0
    BRG Down Counter
    CLKO
    FOSC/4
    SSPADD<6:0>
    SSPM3:SSPM0
    SCL
    Reload
    Control
    Reload
    FCY
    FCY*2
    BRG Value
    FSCL
    (2 Rollovers of BRG)
    10 MHz
    20 MHz
    19h
    400 kHz(1)
    10 MHz
    20 MHz
    20h
    312.5 kHz
    10 MHz
    20 MHz
    3Fh
    100 kHz
    4 MHz
    8 MHz
    0Ah
    400 kHz(1)
    4 MHz
    8 MHz
    0Dh
    308 kHz
    4 MHz
    8 MHz
    28h
    100 kHz
    1 MHz
    2 MHz
    03h
    333 kHz(1)
    1 MHz
    2 MHz
    0Ah
    100 kHz
    1 MHz
    2 MHz
    00h
    1 MHz(1)
    Note 1:
    The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than
    100 kHz) in all details, but may be used with care where higher rates are required by the application.
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