參數(shù)資料
型號： PIC16F785
廠商： Microchip Technology Inc.
英文描述： 20-Pin Flash-Based 8-Bit CMOS Microcontroller with Two-Phase Asychronous Feedback PWM, Dual High-Speed Comparators and Dual Operational Amplifiers
中文描述： 20引腳基于閃存的8兩相異步反饋的PWM，雙高位CMOS微控制器的高速比較器和雙運算放大器
文件頁數(shù)： 103/178頁
文件大?。?/td> 1620K
代理商： PIC16F785
2004 Microchip Technology Inc.
Preliminary
DS41249A-page 101
PIC16F785
14.2
READING THE EEPROM DATA
MEMORY
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD (EECON1<0>), as shown in Example 14-1. The
data is available, in the very next cycle, in the EEDAT
register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read,
or until it is written to by the user (during a write
operation).
EXAMPLE 14-1:
DATA EEPROM READ
14.3
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 14-2.
EXAMPLE 14-2:
BSF
BSF
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
DATA EEPROM WRITE
STATUS,RP0
;Bank 1
STATUS,RP1
EECON1,WREN
;Enable write
INTCON,GIE
;Disable INTs
55h
;Unlock write
EECON2
;
AAh
;
EECON2
;
EECON1,WR
;Start the write
INTCON,GIE
;Enable INTs
The write will not initiate if the above sequence is not
followed exactly (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating the EEPROM. The WREN bit is not cleared
by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR1<7>) register must be cleared by software.
14.4
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 14-3) to the
desired value to be written.
EXAMPLE 14-3:
WRITE VERIFY
14.4.1
USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often). When
variables in one section change frequently, while vari-
ables in another section do not change, it is possible to
exceed the total number of write cycles to the
EEPROM (specification D124) without excceding the
total number of write cycles to a single byte (specifica-
tions D120 and D120A). If this is the case, then an
array refresh must be performed. For this reason, vari-
ables that change infrequently (such as constants, IDs,
calibration, etc.) should be stored in Flash program
memory.
14.5
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the user may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up
Timer
(64 ms
EEPROM write.
duration)
prevents
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
brown-out
power glitch
software malfunction
BSF
BSF
MOVLW
MOVWF
BSF
MOVF
STATUS,RP0 ;Bank 1
STATUS,RP1
CONFIG_ADDR;
EEADR
EECON1,RD
EEDAT,W
;Address to read
;EE Read
;Move data to W
S
R
BSF
BSF
MOVF
STATUS,RP0 ;Bank 1
STATUS,RP1
EEDAT,W
;EEDAT not changed
; from previous write
;YES, Read the
; value written
BSF
EECON1,RD
XORWF
BTFSS
GOTO
EEDAT,W
STATUS,Z
WRITE_ERR
;Is data the same
;No, handle error
;Yes, continue
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參數(shù)描述
PIC16F785-E/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/P 功能描述:8位微控制器 -MCU 14KB 368 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/SO 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-E/SS 功能描述:8位微控制器 -MCU 3.5KB FL 128R 18 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
PIC16F785-I/ML 功能描述:8位微控制器 -MCU 3.5 KB 128 RAM 18I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
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