參數(shù)資料
型號(hào): PIC16F707-I/MV
廠商: Microchip Technology
文件頁數(shù): 95/123頁
文件大?。?/td> 0K
描述: MCU PIC 14KB FLASH 40-UQFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 73
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 363 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-UFQFN 裸露焊盤
包裝: 管件
2010 Microchip Technology Inc.
DS39616D-page 73
PIC18F2331/2431/4331/4431
PDC0L
PWM Duty Cycle #0L Register (lower 8 bits)
0000 0000
PDC0H
UNUSED
PWM Duty Cycle #0H Register (upper 6 bits)
--00 0000
PDC1L
PWM Duty Cycle #1L Register (lower 8 bits)
0000 0000
PDC1H
UNUSED
PWM Duty Cycle #1H Register (upper 6 bits)
--00 0000
PDC2L
PWM Duty Cycle #2L Register (lower 8 bits)
0000 0000
PDC2H
UNUSED
PWM Duty Cycle #2H Register (upper 6 bits)
--00 0000
PDC3L(4)
PWM Duty Cycle #3L Register (lower 8 bits)
0000 0000
PDC3H(4)
UNUSED
PWM Duty Cycle #3H Register (upper 6 bits)
--00 0000
SEVTCMPL
PWM Special Event Compare Register (lower 8 bits)
0000 0000
SEVTCMPH
UNUSED
PWM Special Event Compare Register (upper 4 bits)
---- 0000
PWMCON0
PWMEN2
PWMEN1
PWMEN0
PMOD3
PMOD2
PMOD1
PMOD0
-111 0000
PWMCON1
SEVOPS3
SEVOPS2
SEVOPS1
SEVOPS0
SEVTDIR
UDIS
OSYNC
0000 0-00
DTCON
DTPS1
DTPS0
DT5
DT4
DT3
DT2
DT1
DT0
0000 0000
FLTCONFIG
BRFEN
FLTBS(4)
FLTBMOD(4)
FLTBEN(4)
FLTCON
FLTAS
FLTAMOD
FLTAEN
0000 0000
OVDCOND
POVD7(4)
POVD6(4)
POVD5
POVD4
POVD3
POVD2
POVD1
POVD0
1111 1111
OVDCONS
POUT7(4)
POUT6(4)
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
0000 0000
CAP1BUFH/
VELRH
Capture 1 Register High Byte/Velocity Register High Byte
xxxx xxxx
CAP1BUFL/
VELRL
Capture 1 Register Low Byte/Velocity Register Low Byte
xxxx xxxx
CAP2BUFH/
POSCNTH
Capture 2 Register High Byte/QEI Position Counter Register High Byte
xxxx xxxx
CAP2BUFL/
POSCNTL
Capture 2 Register Low Byte/QEI Position Counter Register Low Byte
xxxx xxxx
CAP3BUFH/
MAXCNTH
Capture 3 Register High Byte/QEI Max. Count Limit Register High Byte
xxxx xxxx
CAP3BUFL/
MAXCNTL
Capture 3 Register Low Byte/QEI Max. Count Limit Register Low Byte
xxxx xxxx
CAP1CON
CAP1REN
CAP1M3
CAP1M2
CAP1M1
CAP1M0
-0-- 0000
CAP2CON
CAP2REN
CAP2M3
CAP2M2
CAP2M1
CAP2M0
-0-- 0000
CAP3CON
CAP3REN
CAP3M3
CAP3M2
CAP3M1
CAP3M0
-0-- 0000
DFLTCON
FLT4EN
FLT3EN
FLT2EN
FLT1EN
FLTCK2
FLTCK1
FLTCK0
-000 0000
TABLE 6-2:
REGISTER FILE SUMMARY (PIC18F2331/2431/4331/4431) (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented.
Note 1:
RA6 and associated bits are configured as port pins in RCIO, ECIO and INTIO2 (with port function on RA6) Oscillator modes only and read
‘0’ in all other oscillator modes.
2:
RA7 and associated bits are configured as port pins in INTIO2 Oscillator mode only and read ‘0’ in all other modes.
3:
Bit 21 of the PC is only available in Test mode and Serial Programming modes.
4:
These registers and/or bits are not implemented on the PIC18F2331/2431 devices and read as ‘0’.
5:
The RE3 port bit is only available for PIC18F4331/4431 devices when the MCLRE fuse (CONFIG3H<7>) is programmed to ‘0’; otherwise, RE3
reads ‘0’. This bit is read-only.
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