參數(shù)資料
型號: PIC16F707-I/MV
廠商: Microchip Technology
文件頁數(shù): 104/123頁
文件大?。?/td> 0K
描述: MCU PIC 14KB FLASH 40-UQFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 73
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 14KB(8K x 14)
程序存儲器類型: 閃存
RAM 容量: 363 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-UFQFN 裸露焊盤
包裝: 管件
2010 Microchip Technology Inc.
DS39616D-page 81
PIC18F2331/2431/4331/4431
7.3
Reading the Data EEPROM
Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available for the very next
instruction cycle; therefore, the EEDATA register can
be read by the next instruction. EEDATA will hold this
value until another read operation, or until it is written to
by the user (during a write operation).The basic
process is shown in Example 7-1.
7.4
Writing to the Data EEPROM
Memory
To write an EEPROM data location, the address must
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle.
The write will not begin if this sequence is not exactly
followed (write 55h to EECON2, write 0AAh to
EECON2, then set WR bit) for each byte. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution (i.e., runaway programs). The WREN bit should
be kept clear at all times, except when updating the
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, EECON1,
EEADR and EEDATA cannot be modified. The WR bit
will be inhibited from being set unless the WREN bit is
set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EEPROM Interrupt Flag bit
(EEIF) is set. The user may either enable this interrupt
or poll this bit. EEIF must be cleared by software.
7.5
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the mem-
ory should be verified against the original value. This
should be used in applications where excessive writes
can stress bits near the specification limit.
7.6
Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built-in. On power-up, the WREN bit is cleared.
Also, the Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
EXAMPLE 7-1:
DATA EEPROM READ
EXAMPLE 7-2:
DATA EEPROM WRITE
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Data Memory Address to read
BCF
EECON1, EEPGD
; Point to DATA memory
BSF
EECON1, RD
; EEPROM Read
MOVF
EEDATA, W
; W = EEDATA
MOVLW
DATA_EE_ADDR
;
MOVWF
EEADR
; Data Memory Address to write
MOVLW
DATA_EE_DATA
;
MOVWF
EEDATA
; Data Memory Value to write
BCF
EECON1, EEPGD
; Point to DATA memory
BCF
EECON1, CFGS
; Access EEPROM
BSF
EECON1, WREN
; Enable writes
BCF
INTCON, GIE
; Disable Interrupts
MOVLW
55h
;
Required
MOVWF
EECON2
; Write 55h
Sequence
MOVLW
0AAh
;
MOVWF
EECON2
; Write 0AAh
BSF
EECON1, WR
; Set WR bit to begin write
BTFSC
EECON1, WR
; Wait for write to complete
GOTO
$-2
;
BSF
INTCON, GIE
; Enable interrupts
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