參數(shù)資料
型號(hào): PIC16F707-I/MV
廠商: Microchip Technology
文件頁數(shù): 54/123頁
文件大?。?/td> 0K
描述: MCU PIC 14KB FLASH 40-UQFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
特色產(chǎn)品: Extreme Low Power (XLP) Microcontrollers
標(biāo)準(zhǔn)包裝: 73
系列: PIC® XLP™ mTouch™ 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 14KB(8K x 14)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 363 x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 14x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-UFQFN 裸露焊盤
包裝: 管件
PIC16(L)F707
DS41418B-page 36
2010-2011 Microchip Technology Inc.
3.6
Time-out Sequence
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit = 1 (PWRT disabled), there will be no
time-out at all. Figure 3-5, Figure 3-6 and Figure 3-7
depict time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 3-6). This is useful for testing purposes or
to synchronize more than one PIC16(L)F707 device
operating in parallel.
Table 3-2 shows the Reset conditions for some special
registers.
3.7
Power Control (PCON) Register
The Power Control (PCON) register has two Status bits
to indicate what type of Reset that last occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable
if
the
brown-out
circuit
is
disabled
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 3.5 “Brown-Out
FIGURE 3-5:
TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1
TABLE 3-4:
TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up from
Sleep
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT + 1024
TOSC
1024 TOSC
TPWRT + 1024
TOSC
1024 TOSC
RC, EC, INTOSC
TPWRT
—TPWRT
——
TPWRT
TOST
VDD
MCLR
Internal POR
PWRT Time-out
OST Time-out
Internal Reset
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