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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | PIC16C765-I/L |
| 寤犲晢锛� | Microchip Technology |
| 鏂囦欢闋佹暩(sh霉)锛� | 79/165闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MCU OTP 8KX14 USB 44PLCC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 27 |
| 绯诲垪锛� | PIC® 16C |
| 鏍稿績铏曠悊鍣細 | PIC |
| 鑺珨灏哄锛� | 8-浣� |
| 閫熷害锛� | 24MHz |
| 閫ｉ€氭€э細 | SCI锛孶ART/USART锛孶SB |
| 澶栧湇瑷�(sh猫)鍌欙細 | 娆犲妾㈡脯(c猫)/寰�(f霉)浣�锛孭OR锛孭WM锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 33 |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄥ閲忥細 | 14KB锛�8K x 14锛� |
| 绋嬪簭瀛樺劜(ch菙)鍣ㄩ鍨嬶細 | OTP |
| RAM 瀹归噺锛� | 256 x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 4.35 V ~ 5.25 V |
| 鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� | A/D 8x8b |
| 鎸暕鍣ㄥ瀷锛� | 澶栭儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 44-LCC锛圝 褰㈠紩绶氾級 |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜闈細 | 636 (CN2011-ZH PDF) |
| 閰嶇敤锛� | AC164309-ND - MODULE SKT FOR PM3 44PLCC ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING 444-1001-ND - DEMO BOARD FOR PICMICRO MCU |
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PIC16C745/765
DS41124C-page 20
Preliminary
2000 Microchip Technology Inc.
Bank 3
180h
INDF(3)
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
181h
OPTION_REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
182h
PCL(3)
Program Counter鈥檚 (PC) Least Significant Byte
0000 0000
183h
STATUS(3)
IRP
RP1
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
184h
FSR(3)
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
185h
鈥�
Unimplemented
鈥�
186h
TRISB
PORTB Data Direction Register
1111 1111
187h
鈥�
Unimplemented
鈥�
188h
鈥�
Unimplemented
鈥�
189h
鈥�
Unimplemented
鈥�
18Ah
PCLATH(1,3)
鈥�
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
18Bh
INTCON(3)
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
18Ch-
18Fh
鈥�
Unimplemented
鈥�
190h
UIR
鈥�
STALL
UIDLE
TOK_DNE
ACTIVITY
UERR
USB_RST --00 0000
--00 0000
191h
UIE
鈥�
STALL
UIDLE
TOK_DNE
ACTIVITY
UERR
USB_RST --00 0000
--00 0000
192h
UEIR
BTS_ERR OWN_ERR WRT_ERR
BTO_ERR
DFN8
CRC16
CRC5
PID_ERR
0000 0000
193h
UEIE
BTS_ERR OWN_ERR WRT_ERR
BTO_ERR
DFN8
CRC16
CRC5
PID_ERR
0000 0000
194h
USTAT
鈥�
ENDP1
ENDP0
IN
鈥�
---x xx--
---u uu--
195h
UCTRL
鈥�
SEO
PKT_DIS
DEV_ATT
RESUME
SUSPND
鈥�
--x0 000-
--xq qqq-
196h
UADDR
鈥�
ADDR6
ADDR5
ADDR4
ADDR3
ADDR2
ADDR1
ADDR0
-000 0000
197h
USWSTAT
SWSTAT7
SWSTAT6
SWSTAT5
SWSTAT4
SWSTAT3
SWSTAT2
SWSTAT1
SWSTAT0 0000 0000 0000 0000
198h
UEP0
鈥�
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
199h
UEP1
鈥�
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Ah
UEP2
鈥�
EP_CTL_DIS EP_OUT_EN EP_IN_EN EP_STALL ---- 0000 ---- 0000
19Bh-
19Fh
Reserved
Reserved, do not use.
0000 0000
TABLE 4-1:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(2)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as 鈥�0鈥�.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note 1:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose contents
are transferred to the upper byte of the program counter.
2:
Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3:
These registers can be addressed from any bank.
4:
The Parallel Slave Port (PORTD and PORTE) is not implemented on the PIC16C745, always maintain these bits clear.
745cov.book Page 20 Wednesday, August 2, 2000 8:24 AM
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| PIC16C765T-I/L | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 256 RAM 33 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
| PIC16C765T-I/PT | 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 14KB 256 RAM 33 I/O RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪(sh铆)閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜(ch菙)鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT |
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