參數(shù)資料
型號: PIC16C54C
廠商: Microchip Technology Inc.
英文描述: EPROM/ROM-Based 8-Bit CMOS Microcontroller(18引腳、12個I/O端口、512位EPROM/ROM的8位CMOS微控制器)
中文描述: 存儲器/基于ROM的8位CMOS微控制器(18引腳,12個的I / O,512位存儲器端口/光盤的8位的CMOS微控制器)
文件頁數(shù): 13/158頁
文件大?。?/td> 1194K
代理商: PIC16C54C
2000 Microchip Technology Inc.
Preliminary
DS30453C-page 13
PIC16C5X
3.1
Clocking Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks, namely Q1, Q2, Q3 and Q4. Internally, the pro-
gram counter is incremented every Q1 and the instruc-
tion is fetched from program memory and latched into
the instruction register in Q4. It is decoded and exe-
cuted during the following Q1 through Q4. The clocks
and instruction execution flow are shown in Figure 3-2
and Example 3-1.
3.2
Instruction Flow/Pipelining
An Instruction Cycle consists of four Q cycles (Q1, Q2,
Q3 and Q4). The instruction fetch and execute are pipe-
lined such that fetch takes one instruction cycle, while
decode and execute takes another instruction cycle.
However, due to the pipelining, each instruction effec-
tively executes in one cycle. If an instruction causes the
program counter to change (e.g.,
GOTO
), then two
cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the Instruction Register in cycle Q1. This instruc-
tion is then decoded and executed during the Q2, Q3
and Q4 cycles. Data memory is read during Q2 (oper-
and read) and written during Q4 (destination write).
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1:
INSTRUCTION PIPELINE FLOW
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC
PC+1
PC+2
Fetch INST (PC)
Execute INST (PC-1)
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is
flushed
from the pipeline, while the new instruction is being fetched and then executed.
1. MOVLW 55H
Fetch 1
Execute 1
Fetch 2
2. MOVWF PORTB
Execute 2
Fetch 3
3. CALL SUB_1
Execute 3
Fetch 4
4. BSF PORTA, BIT3
Flush
Fetch SUB_1 Execute SUB_1
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