
PIC14000
DS40122B-page 86
Preliminary
1996 Microchip Technology Inc.
10.7.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms (with
no
prescaler).
The
time-out
periods
vary
with
temperature, VDD and process variations (see DC
specs). If longer time-out periods are desired, a pres-
caler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION registers. Thus, time-out periods up to
2.3 seconds can be realized. The CLRWDT and SLEEP
instructions clear the WDT and the prescaler, if
assigned to the WDT, and prevent it from timing out and
generating a device RESET.
The TO bit in the status register will be cleared upon a
watchdog timer time-out. The WDT time-out period (no
prescaler) is measured and stored in calibration space
at location 0FD2h.
10.7.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under
worst-case conditions (minimum VDD, maximum
temperature, maximum WDT prescaler) it may take
several seconds before a WDT time-out occurs. Refer
to Section 6.3 for prescaler switching considerations.
10.8
Power Management Options
The PIC14000 has several power management
options to prolong battery lifetime. The SLEEP instruc-
tion halts the CPU and can turn off the on-chip oscilla-
tors. The CPU can be in SLEEP mode, yet the A/D
converter can continue to run. Several bits are included
in the SLPCON register (8Fh) to control power to ana-
log modules.
TABLE 10-6:
SUMMARY OF POWER MANAGEMENT OPTIONS
Function
Summary
CPU Clock
OFF during SLEEP/HIBERNATE mode, ON otherwise
Main Oscillator
ON if NOT in SLEEP mode. In SLEEP mode, controlled by OSCOFF
bit, SLPCON<3>.
Watchdog Timer
Controlled by WDTE, 2007h<2> and HIBEN, SLPCON<7>
Temperature Sensor
Controlled by TEMPOFF, SLPCON<1>
Low-voltage Detector
Controlled by REFOFF, SLPCON<5>
Comparator and
Programmable References
Controlled by CMOFF, SLPCON<2>
A/D Comparator
Controlled by ADOFF, SLPCON<0>
Programmable Current Source
Controlled by ADOFF, SLPCON<0> and ADCON1<7:4>
Slope Reference Voltage Divider
Controlled by ADOFF, SLPCON<0>
Level Shift Networks
Controlled by LSOFF, SLPCON<4>
Bandgap Reference
Controlled by REFOFF, SLPCON<5>
Voltage Regulator Control
Always ON. Does not consume power if unconnected.
Power On Reset
Always ON, except in SLEEP/HIBERNATE mode
Note:
Refer to analog specs for individual peripheral operating currents.