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參數(shù)資料
| 型號： | PIC14000T-20I/SO |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 116/153頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 4KX14 A/D 28SOIC |
| 標準包裝： | 1,600 |
| 系列： | PIC® 14 |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 連通性： | I²C |
| 外圍設備： | POR，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 20 |
| 程序存儲器容量： | 7KB（4K x 14） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 192 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | 斜率 A/D |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 帶卷 (TR) |
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1996 Microchip Technology Inc.
Preliminary
DS40122B-page 65
PIC14000
9.0
OTHER ANALOG MODULES
The PIC14000 has additional analog modules for
mixed signal applications. These include:
bandgap voltage reference
comparators with programmable references
internal temperature sensor
voltage regulator control
9.1
Bandgap Voltage Reference
The bandgap reference circuit is used to generate a
1.2V nominal stable voltage reference for the A/D and
the low-voltage detector. The bandgap reference is
channel 4 of the analog mux. The bandgap reference
voltage is stored in the calibration space EPROM
(See Table 4-2). To enable the bandgap reference
REFOFF (SLPCON<5>) must be cleared.
9.2
Level-Shift Networks
The RA1/AN1 and RA5/AN5 pins have an internal
level-shift network. A current source and resistor are
used to bias the pin voltage by about +0.5V into a range
usable by the A/D converter. The nominal value of bias
current source is 5
A and the resistor is 100 kohms.
The level-shift function can be turned on by clearing the
LSOFF bit (SLPCON<4>) to '0'.
Note:
The minimum voltage permissible at the
RA1/AN1 and RA5/AN5 pins is -0.3V. The
input protection diodes will begin to turn
on beyond -0.3V, introducing signicant
errors in the A/D readings. Under no con-
ditions should the pin voltage fall below
-0.5V.
9.2.1
ZEROING/FILTERING SWITCHES
The RA1/AN1 and RA5/AN5 inputs also have a
matched pair of pass gates useful for current-measure-
ment applications. One gate is connected between the
pin and the level-shift network. The second pass gate
is connected to ground as shown in Figure 9-1. By set-
ting the ADZERO bit (ADCON0<0>), a zero-current
condition is simulated. Subsequent A/D readings are
calculated relative to this zero count from the A/D. This
zeroing of the current provides very high accuracies at
low current values where it is most needed.
For additional noise ltering or for capturing short dura-
tion periodic pulses, an optional lter capacitor may be
connected from the SUM pin to ground (this feature is
available for RA1/AN1 only). This forms an RC network
with the internal 100 kohm (nominal) bias resistor to act
as a low pass lter. The capacitor size can be adjusted
for the desired time constant.
A switch is included between the output from the
RA1/AN1 level-shift network and the SUM pin. This
switch is closed during A/D sampling periods and is
automatically opened during a zeroing operation (if
ADZERO = '1'). If not required in the system, this pin
should be left oating (not connected).
Setting the LSOFF bit (SLPCON<4>) disables the
level-shift networks, so the RA1/AN1 and RA5/AN5
pins can continue to be used as general-purpose ana-
log inputs.
This document was created with FrameMaker404
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