參數(shù)資料
型號(hào): PIC12F635T-I/SN
廠商: Microchip Technology
文件頁(yè)數(shù): 40/74頁(yè)
文件大小: 0K
描述: IC MCU FLASH 1KX14 8SOIC
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
標(biāo)準(zhǔn)包裝: 3,300
系列: PIC® 12F
核心處理器: PIC
芯體尺寸: 8-位
速度: 20MHz
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 5
程序存儲(chǔ)器容量: 1.75KB(1K x 14)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 128 x 8
RAM 容量: 64 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
包裝: 帶卷 (TR)
配用: AC162057-ND - MPLAB ICD 2 HEADER 14DIP
Micrel, Inc.
KSZ8841-PMQL
October 2007
45
M9999-100407-1.5
Bit
Default
R/W
Description
3
00
RO
EECB EEPROM Status Bits
Bit 3: Data receive from EEPROM. This bit directly reflects the value of
the EEDI pin.
2
00
RW
EECB EEPROM Control Bits
Bit 2: Data In to EEPROM. This bit directly controls the device’s the
EEDO pin.
1
00
RW
EECB EEPROM Control Bits
Bit 1: Serial Clock. This bit directly controls the device’s the EESK pin.
0
00
RW
EECB EEPROM Control Bits
Bit 0: Chip Select. This bit directly controls the device’s the EECS pin.
Memory BIST Info Register (Offset 0x0214): MBIR
The following table shows the register bit fields.
Bit
Default
R/W
Description
15-13
0x0
RO
Reserved
12
-
RO
TXMBF TX Memory Bits Finish
When set, it indicates the Memory Built In Self Test has completed for
the TX Memory.
11
-
RO
TXMBFA TX Memory Bits Fail
When set, it indicates the Memory Built In Self Test has failed.
10-5
-
RO
Reserved
4
-
RO
RXMBF RX Memory Bits Finish
When set, it indicates the Memory Built In Self Test has completed for
the RX Memory.
3
-
RO
RXMBFA RX Memory Bits Fail
When set, it indicates the Memory Built In Self Test has failed.
2-0
-
RO
Reserved
Global Reset Register (Offset 0x0216): GRR
This register holds control information programmed by the CPU to control the global soft reset function.
Bit
Default
R/W
Description
15-1
0x00
RO
Reserved
0
RW
Global Soft Reset
1 = Software reset active
0 = Software reset inactive
Soft reset will affect all of the registers except PCI configuration
registers.
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