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| 型號： | PIC12F635T-I/SN |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 32/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 1KX14 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 3,300 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 包裝： | 帶卷 (TR) |
| 配用： | AC162057-ND - MPLAB ICD 2 HEADER 14DIP |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
38
M9999-100407-1.5
Bit
Default
Read/
Write
Description
incoming IP frames at port. Packets received with incorrect IP checksum will
be discarded.
15 - 10
0x00
RO
Reserved
9
0
RW
MRFCE MAC Receive Flow Control Enable
When this bit is set and the KSZ8841-PMQL is in Full Duplex mode, flow
control is enabled and the KSZ8841-PMQL will acknowledge a PAUSE
frame from MAC of the controller, the outgoing packets will be pending in
the transmit buffer until the PAUSE control timer expires.
This field has no meaning in half-duplex mode and should be programmed
to 0.
When this bit is cleared, no flow control is enabled.
8 - 7
00
RO
Reserved
6
0
RW
MRB MAC Receive Broadcast
When set, the MAC receive all broadcast frames.
5
0
RW
MRM MAC Receive Multicast
When set, the MAC receive all multicast frames (including broadcast).
4
0
RW
MRU MAC Receive Unicast
When set, the MAC receive unicast frames that match the 48-bit Station
Address of the MAC.
3
0
RW
MRE MAC DMA Receive Error Frame
When set, the KSZ8841-PMQL will pass the errors frames received to the
host.
Error frames include runt frames, oversized frames, CRC errors.
2
0
RW
MRA MAC DMA Receive All
When set, the KSZ8841-PMQL receives all incoming frames, regardless of
its destination address.
1
0
RW
DMA Receive Multicast Hash-Table Enable
Setting this bit enables the RX function to receive multicast frames that pass
the CRC Hash filtering mechanism.
0
RW
MRE MAC DMA RX Enable
When the bit is set, the DMA RX block is enabled and placed in a running
state. When reset, the receive process is placed in the stopped state after
completing the reception of the current frame. The stop transmission
command is effective only when the reception process is in the running
state.
MAC DMA Transmit Start Command Register (MDTSC Offset 0x0008)
This register is written by the CPU when packets in the data buffer need to be transmitted. The following table shows
the register bit fields.
Bit
Default
Read/
Write
Description
31 - 0
0x00000000
WO
WTSC Transmit Start Command
When written with any value, the Transmit DMA checks for frames to
be transmitted. If no descriptor is available, the transmit process returns
to suspended state. If descriptiors are available, the transmit process
starts or resumes. This bit is self-clearing.
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