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| 型號： | PIC12F635T-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 17/74頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 1KX14 8DFN |
| 標準包裝： | 3,300 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大小： | 128 x 8 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
| 配用： | AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN AC162057-ND - MPLAB ICD 2 HEADER 14DIP XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC |
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Micrel, Inc.
KSZ8841-PMQL
October 2007
24
M9999-100407-1.5
Host Communication
The descriptor lists and data buffers, collectively called the host communication, manage the actions and status related
to buffer management. Commands and signals that control the functional operation of the KSZ8841-PMQL are also
described.
The KSZ8841-PMQL and the driver communicate through the two data structures: Command and status registers
(CSRs) and Descriptor Lists and Data Buffers.
Note: All unused bits of the data structure in this section are reserved and should be written by the driver as zeros.
Host Communication Descriptor Lists and Data Buffers
The KSZ8841-PMQL transfers received data frames to the receive buffer in host memory and transmits data from the
transmit buffers in host memory. Descriptors that reside in the host memory act as pointers to these buffers.
There are two descriptor lists (one for receive and one for transmit) for the MAC DMA. The base address of each list is
written in the TDLB register and in the RDLB register, respectively. A descriptor list is forward linked. The last descriptor
may point back to the first entry to create a ring structure. Descriptors are chained by setting the next address to the
next buffer in both receive and transmit descriptors.
The descriptor lists reside in the host physical memory address space. Each pointer points to one buffer and the
second pointer points to the next descriptor. This enables the greatest flexibility for the host to chain any data buffers
with discontinuous memory location. This eliminates processor-intensive tasks such as memory copying from the host
to memory.
A data buffer contains either an entire frame or part of a frame, but it cannot exceed a single frame. Buffers contain only
data; and buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers.
Data chaining can be enabled or disabled. Data buffers reside in host physical memory space.
Receive Descriptors (RDES0-RDES3)
Receive descriptor and buffer addresses must be Word aligned. Each receive descriptor provides one frame buffer, one
byte count field, and control and status bits.
The following table shows the RDES0 register bit fields.
Bit
Description
31
OWN Own Bit
When set, indicates that the descriptor is owned by the KSZ8841-PMQL.
When reset, indicates that the descriptor is owned by the host. The KSZ8841-PMQL clears
this bit either when it completes the frame reception or when the buffers that are associated
with this descriptor are full.
30
FS First Descriptor
When set, indicates that this descriptor contains the first buffer of a frame.
If the buffer size of the first buffer is 0, the next buffer contains the beginning of the frame.
29
LS Last Descriptor
When set, indicates that the buffer pointed by this descriptor is the last buffer of the frame.
28
IPE IP Checksum Error
When set, indicates that the received frame is an IP packet and its IP checksum field does
not match.
This bit is valid only when last descriptor is set.
27
TCPE TCP Checksum Error
When set, indicates that the received frame is a TCP/IP packet and its TCP checksum field
does not match.
This bit is valid only when last descriptor is set.
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