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參數(shù)資料
| 型號： | PIC12F1501-I/MF |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 9/33頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 1.75KB FLASH 8-DFN |
| 標準包裝： | 120 |
| 系列： | PIC® 12F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 20MHz |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 5 |
| 程序存儲器容量： | 1.75KB（1K x 14） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 64 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.3 V ~ 5.5 V |
| 數(shù)據(jù)轉換器： | A/D 4x10b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-VDFN 裸露焊盤 |
| 包裝： | 管件 |
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2011 Microchip Technology Inc.
Preliminary
DS41615A-page 17
PIC12(L)F1501
3.1.1.2
Indirect Read with FSR
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete. Example 3-2 demonstrates access-
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
3.2
Data Memory Organization
The data memory is partitioned into 32 memory banks
with 128 bytes in each bank. Each bank consists of
(Figure 3-2):
12 core registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers
(FSR).
See
Addressing” for more information.
Data memory uses a 12-bit address. The upper 7 bits
of the address define the Bank address and the lower
5 bits select the registers/RAM in that bank.
3.2.1
CORE REGISTERS
The core registers contain the registers that directly
affect the basic operation. The core registers occupy
the first 12 addresses of every data memory bank
(addresses x00h/x08h through x0Bh/x8Bh). These
registers are listed below in Table 3-2. For detailed
information, see Table 3-4.
TABLE 3-2:
CORE REGISTERS
constants
RETLW DATA0
;Index0 data
RETLW DATA1
;Index1 data
RETLW DATA2
RETLW DATA3
my_function
;… LOTS OF CODE…
MOVLW
LOW constants
MOVWF
FSR1L
MOVLW
HIGH constants
MOVWF
FSR1H
MOVIW
0[FSR1]
;THE PROGRAM MEMORY IS IN W
Addresses
BANKx
x00h or x80h
INDF0
x01h or x81h
INDF1
x02h or x82h
PCL
x03h or x83h
STATUS
x04h or x84h
FSR0L
x05h or x85h
FSR0H
x06h or x86h
FSR1L
x07h or x87h
FSR1H
x08h or x88h
BSR
x09h or x89h
WREG
x0Ah or x8Ah
PCLATH
x0Bh or x8Bh
INTCON
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