參數(shù)資料
型號(hào)： PIC12F1501-I/MF
廠商： Microchip Technology
文件頁(yè)數(shù)： 17/33頁(yè)
文件大小： 0K
描述： IC MCU 8BIT 1.75KB FLASH 8-DFN
標(biāo)準(zhǔn)包裝： 120
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 64 x 8
電壓 - 電源 (Vcc/Vdd)： 2.3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-VDFN 裸露焊盤
包裝： 管件
2007 Microchip Technology Inc.
DS39605F-page 23
PIC18F1220/1320
3.3.1
PRI_IDLE MODE
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary system
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered by setting the IDLEN bit,
clearing the SCS bits and executing a SLEEP instruc-
tion. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified in Configuration Register 1H. The OSTS bit
remains set in PRI_IDLE mode (see Figure 3-3).
When a wake event occurs, the CPU is clocked from
the primary clock source. A delay of approximately
10
μs is required between the wake event and code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 3-4).
FIGURE 3-3:
TRANSITION TIMING TO PRI_IDLE MODE
FIGURE 3-4:
TRANSITION TIMING FOR WAKE FROM PRI_IDLE MODE
Q1
Peripheral
Program
PC
PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program
PC
CPU Clock
PC + 2
Q1
Q3
Q4
Clock
Counter
Q2
Wake Event
CPU Start-up Delay
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