參數(shù)資料
型號(hào): PIC12CR509A
廠商: Microchip Technology Inc.
英文描述: 8-Pin, 8-Bit CMOS Microcontrollers
中文描述: 8引腳,8位CMOS微控制器
文件頁(yè)數(shù): 91/113頁(yè)
文件大?。?/td> 1604K
代理商: PIC12CR509A
1999 Microchip Technology Inc.
DS40139E-page 91
PIC12C5XX
TABLE 13-8:
EEPROM MEMORY BUS TIMING REQUIREMENTS - PIC12CE5XX
ONLY
.
AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature 0
°
C
T
A
+70
°
C, Vcc = 3.0V to 5.5V (commercial)
–40
°
C
T
A
+85
°
C, Vcc = 3.0V to 5.5V (industrial)
–40
°
C
T
A
+125
°
C, Vcc = 4.5V to 5.5V (extended)
Operating Voltage V
DD
range is described in Section 13.1
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
F
CLK
100
100
400
1000
1000
300
300
3500
3500
900
250
kHz
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 1)
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 2)
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
4.5V
Vcc
5.5V (E Temp range)
3.0V
Vcc
4.5V
4.5V
Vcc
5.5V
(Note 1), CB
100 pF
Clock high time
T
HIGH
4000
4000
600
4700
4700
1300
4000
4000
600
4700
4700
600
0
250
250
100
4000
4000
600
4700
4700
1300
20+0.1
CB
ns
Clock low time
T
LOW
ns
SDA and SCL rise time
(Note 1)
T
R
ns
SDA and SCL fall time
START condition hold time
T
F
ns
ns
T
HD
:
STA
START condition setup time
T
SU
:
STA
ns
Data input hold time
Data input setup time
T
HD
:
DAT
T
SU
:
DAT
ns
ns
STOP condition setup time
T
SU
:
STO
ns
Output valid from clock
(Note 2)
T
AA
ns
Bus free time: Time the bus must
be free before a new transmis-
sion can start
Output fall time from V
IH
minimum to V
IL
maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time
Endurance
Note 1:
Not 100% tested. CB = total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on Microchip’s website.
T
BUF
ns
T
OF
ns
T
SP
50
ns
(Notes 1, 3)
T
WC
1M
4
ms
cycles
25
°
C, V
CC
= 5.0V, Block Mode (Note 4)
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