參數(shù)資料
型號(hào)： PIC12C671-10/P
廠商： Microchip Technology
文件頁數(shù)： 35/129頁
文件大小： 0K
描述： IC MCU OTP 1KX14 A/D 8DIP
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝： 60
系列： PIC® 12C
核心處理器： PIC
芯體尺寸： 8-位
速度： 10MHz
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 1.75KB（1K x 14）
程序存儲(chǔ)器類型： OTP
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 8-DIP（0.300"，7.62mm）
包裝： 管件
配用： ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
1999 Microchip Technology Inc.
DS30561B-page 13
PIC12C67X
TABLE 4-1:
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
Resets(3)
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
03h(1)
STATUS
IRP(4)
RP1(4)
RP0
TO
PD
ZDC
C
0001 1xxx
000q quuu
04h(1)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
GPIO
SCL(5)
SDA(5)
GP5
GP4
GP3
GP2
GP1
GP0
11xx xxxx
11uu uuuu
06h
—
Unimplemented
—
07h
—
Unimplemented
—
08h
—
Unimplemented
—
09h
—
Unimplemented
—
0Ah(1,2)
PCLATH
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh(1)
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 000x
0000 000u
0Ch
PIR1
—ADIF
—
-0-- ----
0Dh
—
Unimplemented
—
0Eh
—
Unimplemented
—
0Fh
—
Unimplemented
—
10h
—
Unimplemented
—
11h
—
Unimplemented
—
12h
—
Unimplemented
—
13h
—
Unimplemented
—
14h
—
Unimplemented
—
15h
—
Unimplemented
—
16h
—
Unimplemented
—
17h
—
Unimplemented
—
18h
—
Unimplemented
—
19h
—
Unimplemented
—
1Ah
—
Unimplemented
—
1Bh
—
Unimplemented
—
1Ch
—
Unimplemented
—
1Dh
—
Unimplemented
—
1Eh
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
ADCS1
ADCS0
reserved
CHS1
CHS0
GO/DONE
reserved
ADON
0000 0000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
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