Pericom Semiconductor Each register in the UART Register Block" />
參數(shù)資料
型號(hào)： PI7C9X7954AFDE
廠商： Pericom
文件頁(yè)數(shù)： 48/70頁(yè)
文件大?。?/td> 0K
描述： IC PCIE-TO-UART BRIDGE 128LQFP
標(biāo)準(zhǔn)包裝： 90
應(yīng)用： PCIe至UART橋接
接口： 高級(jí)配置電源接口（ACPI）
電源電壓： 1.8V, 3.3V
封裝/外殼： 128-LQFP 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 128-LQFP（14x14）
包裝： 托盤(pán)
安裝類(lèi)型： 表面貼裝
PI7C9X7954
PCI Express Quad UART
Datasheet
Page 52 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
Each register in the UART Register Block can be access by adding an offset to the UART Memory Base
Address. The following table lists the arrangement of the registers in the UART Register Block in memory
mode.
Table 7-4 Memory-Map mode
Offset
Register Name
Mnemonic
Register Type
UART Memory Base Address + 00h
Receive Holding Register
RHR
RO
UART Memory Base Address + 00h
Transmit Holding Register
THR
WO
UART Memory Base Address + 01h
Interrupt Enable Register
IER
RW
UART Memory Base Address + 02h
Interrupt Status Register
ISR
RO
UART Memory Base Address + 02h
FIFO Control Register
FCR
WO
UART Memory Base Address + 04h
Line Control Register
LCR
RW
UART Memory Base Address + 04h
Modem Control Register
MCR
RW
UART Memory Base Address + 05h
Line Status Register
LSR
RO
UART Memory Base Address + 06h
Modem Status Register
MSR
RO
UART Memory Base Address + 07h
Special Function Register
SFR
RW
UART Memory Base Address + 08h
Divisor Latch Low
DLL
WO
UART Memory Base Address + 09h
Divisor Latch High
DLH
WO
UART Memory Base Address + 0Ah
Enhanced Function Register
EFR
RW
UART Memory Base Address + 0Bh
XON 1 Character/Special
Character 1
XON1
RW
UART Memory Base Address + 0Ch
XON 2 Character/Special
Character 2
XON2
RW
UART Memory Base Address + 0Dh
XOFF 1 Character/Special
Character 3
XOFF1
RW
UART Memory Base Address + 0Eh
XOFF 2 Character/Special
Character 3
XOFF2
RW
UART Memory Base Address + 0Fh
ACR Register
ASR
RW
UART Memory Base Address + 10h
Transmitter Interrupt Trigger
Level
TTL
RW
UART Memory Base Address + 11h
Receiver Interrupt Trigger Level
RTL
RW
UART Memory Base Address + 12h
Automatic Flow control lower
trigger level
FCL
RW
UART Memory Base Address + 13h
Automatic Flow control lower
higher level
FCH
RW
UART Memory Base Address + 14h
Baud rate Prescale
CPR
RW
UART Memory Base Address + 15h
Receive FIFO Data Counter /
Line Status Register Counter
RFD / LSR
Counter
RO
UART Memory Base Address + 16h
Transmit FIFO Data Counter /
Sample Clock Register
TFD
Counter /
SCR
RW
UART Memory Base Address + 17h
Global Register of LSR
GLSR
RW
UART Memory Base Address + 100h
~17Fh
UART0 FIFO DATA Register.
Use this register to map FIFO
data content.
FIFO_D
RW
UART Memory Base Address + 180h
~1FFh
UART0 FIFO DATA LSR
Register. Use this register to map
FIFO data relative LSR content.
FIFO_LSR
RW
7.2.1.
RECEIVE HOLDING REGISTER – OFFSET 00h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Rx Holding
RO
When data are read from the Receive Holding Register (RHR),
they are removed from the top of the receiver’s associated
FIFOs, which holds a queue of data received by the receiver.
Data read from the RHR when the FIFOs are empty are invalid.
The Line Status Register (LSR) indicates the full or empty status
of the FIFOs.
Reset to 00h.
13-0093
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