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| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 20/70頁 |
| 文件大小： | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 27 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
BIT
FUNCTION
TYPE
DESCRIPTION
Reset to 0b.
7
Wait Cycle Control
RO
Does not apply to PCI Express. Must be hardwired to 0b.
8
SERR# enable
RW
This bit, when set, enables reporting of Non-fatal and Fatal errors
detected by the device to the Root Complex.
Reset to 0b.
9
Fast Back-to-Back
Enable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
10
Interrupt Disable
RW
Controls the ability of the I/O bridge to generate INTx interrupt
Messages.
Reset to 0b.
15:11
Reserved
RO
Reset to 00000b.
6.2.4.
STATUS REGISTER – OFFSET 04h
BIT
FUNCTION
TYPE
DESCRIPTION
18:16
Reserved
RO
Reset to 000b.
19
Interrupt Status
RO
Indicates that an INTx interrupt Message is pending internally to the
device.
Reset to 0b.
20
Capabilities List
RO
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1b.
21
66MHz Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
22
Reserved
RO
Reset to 0b.
23
Fast Back-to-Back
Capable
RO
Does not apply to PCI Express. Must be hardwired to 0b.
24
Master Data Parity
Error
RWC
It is not implemented. Hardwired to 0b.
26:25
DEVSEL# Timing
RO
Does not apply to PCI Express. Must be hardwired to 0b.
27
Signaled Target
Abort
RWC
Set to 1 (by a completer) whenever completing a request in the I/O
bridge side using Completer Abort Completion Status.
Reset to 0b.
28
Received Target
Abort
RWC
It is not implemented. Hardwired to 0b.
29
Received Master
Abort
RWC
It is not implemented. Hardwired to 0b.
30
Signaled System
Error
RWC
Set to 1 when the I/O bridge sends an ERR_FATAL or
ERR_NONFATAL Message, and the SERR Enable bit in the
Command register is 1.
Reset to 0b.
31
Detected Parity
Error
RWC
Set to 1 whenever the I/O bridge receives a Poisoned TLP.
Reset to 0b.
6.2.5.
REVISION ID REGISTER – OFFSET 08h
BIT
FUNCTION
TYPE
DESCRIPTION
7:0
Revision
RO
Indicates revision number of the I/O bridge. The default value may
be changed by auto-loading from EEPROM.
Reset to 00h.
6.2.6.
CLASS CODE REGISTER – OFFSET 08h
13-0093
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