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參數(shù)資料
| 型號： | PI7C9X7954AFDE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 23/70頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PCIE-TO-UART BRIDGE 128LQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 應(yīng)用： | PCIe至UART橋接 |
| 接口： | 高級配置電源接口（ACPI） |
| 電源電壓： | 1.8V, 3.3V |
| 封裝/外殼： | 128-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 128-LQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
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PI7C9X7954
PCI Express Quad UART
Datasheet
Page 3 of 70
May 2013 – Revision 1.4
Pericom Semiconductor
REVISION HISTORY
Date
Revision Number
Description
10/31/07
0.1
Preliminary Datasheet
Fixed the diagrams
Corrected Chapter 4.2 Pin Description (RREF, GPIO[7])
Updated Chapter 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver
Setting, 6.2.41 GPIO Control Register )
Revised Chapter 7.1 Registers in I/O Mode
Updated Chapter 11 Ordering Info
12/20/2007
0.2
Updated Chapter 4 Pin Assignment (description for shared pins added,
MODE_SEL changed to DRIVER_SEL)
Updated Chapter 6 PCI Express Register Description
Updated Chapter 7 UART Register Description
Updated Chapter 8 EEPROM Interface
4/22/08
0.3
Updated 1 Features (Clock prescaler, Data frame size, Power Dissipation)
Corrected 3 General Description
Updated 4 Pin Assignment (description for shared pins added, MODE_SEL
changed to DRIVER_SEL, VAUX changed to VDDCAUX, WAKEUP_L,
CLKINP, CLKINN)
Added 5.2.4 Mode Selection, 5.2.5 450/550 Mode, 5.2.6 Enhanced 550 Mode,
5.2.7 Enhanced 950 Mode
Corrected 5.2.8 Transmit and Receive FIFOs, 5.2.9 Automated Flow Control
Modified 5.2.12 Baud Rate Generation
Updated 6 PCI Express Register Description (6.2.36, 6.2.42)
Updated Format (6.2.20, 6.2.36, 6.2.54, 6.2.55, 6.2.57)
Updated Chapter 7 UART Register Description (7.1.6 LCR Bit[5:0], 7.1.7 MCR
Bit[5] and Bit[7], 7.1.9 MSR Bit[3:0], 7.2.6 LCR Bit[5:0], 7.2.7 MCR Bit[5] and
Bit[7], 7.2.9 MSR Bit[3:0], 7.2.11 DLL, 7.2.12 DLH, 7.2.13 EFR, 7.2.18 ACR
Bit[7:2], 7.2.23 CPRM)
Updated Chapter 8.3 EEPROM Space Address Map And Description (00h, 0Ah,
40h)
Added Chapter 9 Electrical Specification
Corrected 9.2 DC Specification
Updated 9.3 AC Specification
Added 10 Clock Scheme
8/13/08
0.4
Updated Chapter 1 Features (added Industrial Temperature Range)
Updated 9.1 Absolute Maximum Ratings: Ambient Temperature with power
applied
11/25/08
1.0
Updated 7.1.13 Sample Clock Register and 7.2.27 Sample Clock Register
Updated Chapter 12 Ordering Information
Removed “Preliminary” and “Confidential” references
3/6/09
1.1
Corrected Figure 3-1 PI7C9X7954 Block Diagram (SYN_UART_CLK removed)
Corrected Section 4.2.1 UART Interface (SYNCLK_IN_EN and
SYN_UART_CLK removed)
Corrected Figure 5-2 Internal Loopback in PI7C7954
Corrected Figure 5-3 Crystal Oscillator as the Clock Source (14.7456 MHz)
Corrected Section 7.1.7 Modem Control Register (Bit[5]), 7.1.10 Special
Function Register (Bit[4]), 7.2.7 Modem Control Register (Bit[5]), 7.2.10
Special Function Register (Bit[4]), 7.2.29 Receive FIFO Data Registers, 7.2.30
Transmit FIFO Data Register, 7.2.31
4/21/09
1.2
Added internal pull-up and pull-down information to UART Interface, System
Interface, Test Signal, and EEPROM pins in Section 4.
9/24/09
1.3
Updated Figure 5-3 Crystal Oscillator as the Clock Source
Updated Section 6.2.24 Message Signaled Interrupt (MSI) Next Item Pointer 8Ch
Added Section 6.2.25 Message Address Register – Offset 90h
Added Section 6.2.26 Message Upper Address Register – Offset 94h
Added Section 6.2.27 Message Data Register – Offset 98h
5/15/13
1.4
Updated Section 4.1 Pin List (SR_DO and SR_DI)
Updated Section 4.2.5 EEPROM Interface (SR_DO and SR_DI)
13-0093
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