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參數(shù)資料
| 型號(hào)： | PI7C8150B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁數(shù)： | 96/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 96 of 115
July 31, 2003 – Revision 1.031
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Reset to 0
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
attempts.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
attempts.
Reset to 0
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
24
attempts.
Reset to 0.
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
16
Address Parity
Error
R/WC
17
Posted Write
Data Parity Error
R/WC
18
Posted Write
Non-delivery
R/WC
19
Target Abort
during Posted
Write
R/WC
20
Master Abort
during Posted
Write
R/WC
21
Delayed Write
Non-delivery
R/WC
22
Delayed Read –
No Data from
Target
R/WC
23
Delayed
Transaction
Master Timeout
R/WC
14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
0
Function
Reserved
Type
R/O
Description
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150B’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
1
Primary MEMR
Command Alias
Enable
R/W
2
Primary MEMW
Command Alias
Enable
R/W
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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