參數(shù)資料
型號： PI7C8150B
英文描述： PCI Bridge | Asynchronous 2-Port PCI Bridge
中文描述： PCI橋|異步2端口PCI橋
文件頁數(shù)： 60/115頁
文件大?。?/td> 879K
代理商： PI7C8150B
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 60 of 115
July 31, 2003 – Revision 1.031
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
!
PI7C8150B sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
!
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
!
The SERR_L enable bit is set in the command register.
!
The parity error response bit is set in the bridge control register of the
secondary interface.
!
The parity error response bit is set in the command register of the primary
interface.
!
PI7C8150B has not detected the parity error on the secondary (initiator)
bus, which the parity error is not forwarded from the secondary bus to the
primary bus.
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR_L will not be
asserted.
6.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150B to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8150B to data parity errors according to the status bits that PI7C8150B sets and the
signals that it asserts.
Table 6-1 shows setting the detected parity error bit in the status register, corresponding to
the primary interface. This bit is set when PI7C8150B detects a parity error on the primary
interface.
Table 6-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
x / x
0
0
1
0
1
0
0
0
1
0
0
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150B-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8150BEVB 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8150BMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMA-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BMAE 功能描述:外圍驅(qū)動器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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