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參數(shù)資料
| 型號(hào)： | PI7C8150B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁(yè)數(shù)： | 83/115頁(yè) |
| 文件大小： | 879K |
| 代理商： | PI7C8150B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 83 of 115
July 31, 2003 – Revision 1.031
Bit
Function
Type
Description
Controls the ability to perform address / data stepping
0: disable address/data stepping (affects primary and secondary)
1: enable address/data stepping (affects primary and secondary)
Reset to 0
Controls the enable for the P_SERR_L pin
0: disable the P_SERR_L driver
1: enable the P_SERR_L driver
Reset to 0
Controls 7C8150’s ability to generate fast back-to-back transactions
to different devices on the primary interface.
0: no fast back-to-back transactions
1: enable fast back-to-back transactions
Reset to 0
Returns 000000 when read
7
Wait Cycle
Control
R/O
8
P_SERR_L
enable
R/W
9
Fast Back-to-
Back Enable
R/W
15:10
Reserved
R/O
14.1.4
STATUS REGISTER – OFFSET 04h
Bit
19:16
20
Function
Reserved
Capabilities List
Type
R/O
R/O
Description
Reset to 0
Set to 1 to enable support for the capability list (offset 34h is the
pointer to the data structure)
Reset to 1
Set to 1 to enable 66MHz operation on the primary interface
Reset to 1
Reset to 0
Set to 1 to enable decoding of fast back-to-back transactions on the
primary interface to different targets
Reset to 1
Set to 1 when P_PERR_L is asserted and bit 6 of command register
is set
Reset to 0
DEVSEL_L timing (medium decoding)
00: fast DEVSEL_L decoding
01: medium DEVSEL_L decoding
10: slow DEVSEL_L decoding
11: reserved
Reset to 01
Set to 1 (by a target device) whenever a target abort cycle occurs
Reset to 0
Set to 1 (by a master device) whenever transactions are terminated
with target aborts
Reset to 0
Set to 1 (by a master) when transactions are terminated with Master
Abort
Reset to 0
21
66MHz Capable
R/O
22
23
Reserved
Fast Back-to-
Back Capable
R/O
R/O
24
Data Parity Error
Detected
R/WC
26:25
DEVSEL_L
timing
R/O
27
Signaled Target
Abort
R/WC
28
Received Target
Abort
R/WC
29
Received Master
Abort
R/WC
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PDF描述 |
|---|---|
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C8152 | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C8154B | 2 PORT 64 BIT 66MHZ PCI TO PCI BRIDGE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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