參數(shù)資料
型號(hào): PI2EQX6864-AZFE
廠商: Pericom
文件頁數(shù): 17/18頁
文件大?。?/td> 0K
描述: IC REDRIVER 56TQFN
標(biāo)準(zhǔn)包裝: 1
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: SAS2,SATA,XAUI
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(5x11)
包裝: 管件
8
www.pericom.com
PS9103
07/21/10
All trademarks are property of their respective owners.
PI2EQX6864-A
6.5Gbps 4-Lane SAS2/SATA/XAUI 2.0 ReDriver
The Channel Input Disable register, provides control over the input buffer of each channel independently. When and INDIS_xy
bit is logic 1, then the input buffer is switched off and the input termination is high impedance. This feature can be used for PCB
testing, and when only one input is used during Loopback as a demux function. When INDIS_xy is at a logic 0 state then the input
buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Bit
7
6
5
4
3
2
1
0
Name
ODIS_A0 ODIS_B0 ODIS_A1 ODIS_B1 ODIS_A2 ODIS_B2 ODIS_A3 ODIS_B3
Type
R/W
Power-on
State
0
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently. When and OUTDIS_xy
bit is logic 1, then the output buffer is switched off and the termination is high impedance. This feature can be used for PCB testing,
and when only one output is used during Loopback as a mux function. When INDIS_xy is at a logic 0 state then the input buffer is
enabled (normal operating mode).
BYTE 5 - Reserved
Reseved Byte 5 is visible via the I2C interface. This is a R/W byte with an undefined initial power-on state. This byte is reserved for
future use and should not be written to.
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
7
6
5
4
3
2
1
0
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
Power-on
State
PD#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When PD_xy# is logic 0 the
channel is turned off. When PD_xy# is 1 then the channel is enabled for normal operation.
BYTE 7 - Reserved
Reseved Byte 7 is visible via the I2C interface. This is a R/W byte with an undefined initial power-on state. This byte is reserved for
future use and should not be written to.
2010-0197
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