參數(shù)資料
型號(hào): PI2EQX6864-AZFE
廠商: Pericom
文件頁(yè)數(shù): 15/18頁(yè)
文件大?。?/td> 0K
描述: IC REDRIVER 56TQFN
標(biāo)準(zhǔn)包裝: 1
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動(dòng)器
驅(qū)動(dòng)器/接收器數(shù): 2/2
規(guī)程: SAS2,SATA,XAUI
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(5x11)
包裝: 管件
6
www.pericom.com
PS9103
07/21/10
All trademarks are property of their respective owners.
PI2EQX6864-A
6.5Gbps 4-Lane SAS2/SATA/XAUI 2.0 ReDriver
I2C Operation
The integrated I2C interface operates as a slave device, supporting standard rate operation of 100Kbps, with 7-bit addressing mode,
with support for offset byte-write and read. The data byte format is 8 bit bytes. The bytes must be accessed in sequential order from
the lowest to the highest byte with the ability to stop after any complete byte has been transferred. Address bits A4, A1 and A0 are
programmable to support multiple chips environment. The data is loaded until a Stop sequence is issued.
Note that the I2C inputs, SCL and SDA operate at 1.2V logic levels and are 3.3V tolerant.
Configuration Register Summary
Byte Mnemonic Function
0
SIG
Signal Detect, indicates valid input signal level
1
RSVD
Reserved For Future Use
2
LBEC
Loopback and Emphasis Control, provides for control of the loopback function and emphasis mode (pre-
emphasis or de-emphasis)
3
INDIS
Channel Input Disable, controls whether a channel input buffer is enabled or disabled
4
OUTDIS
Channel Output Disable, controls whether a channel output buffer is enabled or disabled
5
RSVD
Reserved For Future Use
6
PWR
Power Down Control, enables power down for each channel individually
7
RSVD
Reserved For Future Use
8
AEOC
A-Channels Equalizer and Output Control
9
AEOC
B-Channels Equalizer and Output Control
10
RSVD
Reserved
11
RSVD
Reserved
2010-0197
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