參數資料
型號: PI2EQX6864-AZFE
廠商: Pericom
文件頁數: 11/18頁
文件大?。?/td> 0K
描述: IC REDRIVER 56TQFN
標準包裝: 1
系列: ReDriver™
類型: 轉接驅動器
驅動器/接收器數: 2/2
規(guī)程: SAS2,SATA,XAUI
電源電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 56-WFQFN 裸露焊盤
供應商設備封裝: 56-TQFN-EP(5x11)
包裝: 管件
2
www.pericom.com
PS9103
07/21/10
All trademarks are property of their respective owners.
PI2EQX6864-A
6.5Gbps 4-Lane SAS2/SATA/XAUI 2.0 ReDriver
Pin Description
Pin #
Pin Name
Type
Description
Data Signals
2
3
A0RX+,
A0RX-
I
CML inputs for Channel A0, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
48
47
A0TX+,
A0TX-
O
CML outputs for Channel A0, with internal 50-Ohm pull-up. Goes to high-
impedance during power-down (PD#=0).
7
8
A1RX+,
A1RX-
I
CML inputs for Channel A1, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
43
42
A1TX+,
A1TX-
O
CML outputs for Channel A1, with internal 50-Ohm pull-up. Goes to high-im-
pedance during power-down (PD#=0).
12
13
A2RX+,
A2RX-
I
CML inputs for Channel A2, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
38
37
A2TX+,
A2TX-
O
CML outputs for Channel A2, with internal 50-Ohm pull-up. Goes to high-
impedance during power-down (PD#=0).
17
18
A3RX+,
A3RX-
I
CML inputs for Channel A3 with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
33
32
A3TX+,
A3TX-
O
CML outputs for Channel A3, with internal 50-Ohm pull-up. Goes to high-
impedance during power-down (PD#=0).
46
45
B0RX+,
B0RX-
I
CML inputs for Channel B0, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
4
5
B0TX+,
B0TX-
O
CML outputs for Channel B0, with internal 50-Ohm pull-up. Goes to high-im-
pedance during power-down (PD#=0).
41
40
B1RX+,
B1RX-
I
CML inputs for Channel B1, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
9
10
B1TX+,
B1TX-
O
CML outputs for Channel B1, with internal 50-Ohm pull-up. Goes to high-im-
pedance during power-down (PD#=0).
36
35
B2RX+,
B2RX-
I
CML inputs for Channel B2, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
14
15
B2TX+,
B2TX-
O
CML outputs for Channel B2, with internal 50-Ohm pull-up. Goes to high-im-
pedance during power-down (PD#=0).
31
30
B3RX+,
B3RX-
I
CML inputs for Channel B3, with internal 50-Ohm pull-down. Goes to high-
impedance during power-down (PD#=0).
19
20
B3TX+,
B3TX-
O
CML outputs for Channel B3, with internal 50-Ohm pull-up. Goes to high-im-
pedance during power-down (PD#=0).
Control Signals
26, 27, 25
A0, A1, A4
I
I2C programmable address bit A0, A1 and A4.
28
LB#
I
Input with internal 100K-Ohm pull-up resistor. LB# = High or open for normal
operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX.
22
SIG_B
0
Signal detect output for channel B. SIG_B indicates a valid input signal which is
> Vth at the differential inputs. With 100K-Ohm internal pull up.
23
MODE
I
A LVCMOS high level disables I2C operation. With 100K-Ohm internal pull up.
24, 54
NC
Do Not Connect (Reserved for future use.)
(Continued)
2010-0197
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