參數(shù)資料
型號: PI2EQX5804CNJE
廠商: Pericom
文件頁數(shù): 10/23頁
文件大?。?/td> 0K
描述: IC PCI-E REDRIVER 100LBGA
標(biāo)準(zhǔn)包裝: 176
系列: ReDriver™
類型: 轉(zhuǎn)接驅(qū)動器
Tx/Rx類型: CML
電容 - 輸入: 50pF
電源電壓: 1.15 V ~ 1.25 V
電流 - 電源: 800mA
安裝類型: 表面貼裝
封裝/外殼: 100-BGA
供應(yīng)商設(shè)備封裝: 100-LBGA(11x11)
包裝: 托盤
18
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe 2.0 ReDriver with
Equalization & Emphasis
Equalizer
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
JRS-T
Residual jitter
Total
0.3
Ulp-p
JRS-D
Residual jitter
Deterministic
0.2
Ulp-p
JRM
Random jitter
Note 2
1.5
psrms
Notes
1. K28.7 pattern is applied differentially at point A as shown in AC test circuit (see gure).
2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 × RJ + DJ) where RJ is random RMS jitter and DJ is maximum
deterministic jitter. Signal source is a K28.5 ± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or
equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its
equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. Jitter is measured at 0V
at point C of the AC test circuit (see gure).
CML Transmitter Output (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ZOUT
Output resistance
Single ended
40
50
60
Ohms
ZTX-DIFF-DC
DC Differential TX Imped-
ance
80
100
120
Ohms
VDIFFP
Output Voltage Swing, Dif-
ferential
|VTX-D+ - VTX-D-|
200
800
mVp-p
VTX-DIFFP-P
Differential Peak-to-peak
Ouput Voltage
VTX-DIFFP-P = 2 * | VTX-D+ -
VTX-D- |
0.4
1.6
V
VTX-C
Common-Mode Voltage
| VTX-D+ + VTX-D- | / 2
VDD- 0.3
V
tF, tR
Transition Time
20% to 80% (3)
150
ps
CTX(1)
AC Coupling Capacitor
75
200
nF
Note:
1. Recommended external blocking capacitor.
Digital I/O DC Specications (VDD = 1.2V ± 0.05V, TA = 0 to 70°C)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIH
DC input logic high
VDD/2 +0.2
VDD+0.3
V
VIL
DC input logic low
-0.3
VDD/2 -0.2
V
VOH
DC output logic high
IOH = 4mA
VDD-0.4
V
VOL
DC output logic low
IOL = 4mA
0.4
V
Vhys
Hysteresis of Schmitt trigger input
0.2
V
IIH(1)
Input high current
100
μA
IIL1(2)
Input low current
-20
μA
IIL2(3)
Input low current
-20
μA
Notes:
1. Includes input signals A1, A2, A4, Dx_[A:B], DE_[A:B], LB#, MODE#, PD#, RESET#, RXD_[A:B], Sx_[A:B], SCL, SDA, SEL_x[A:B]
2. For control inputs without pullups: A1, A2, A4, SCL, SDA
3. Control inputs with pull-ups include: Dx_[A:B], DE_[A:B], LB#, MODE#, PD#, RESET#, RXD_[A:B], Sx_[A:B], SEL_x[A:B]
09-0001
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