
Philips Semiconductors
Objective specification
PowerMOS transistor
PHP2N40E
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
field-effect power transistor in a
plastic
envelope
avalanche energy capability, stable
blocking voltage, fast switching and
high thermal cycling performance
withlowthermalresistance.Intended
for use in Switched Mode Power
Supplies
(SMPS),
circuits
and
general
switching applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
featuring
high
V
DS
I
D
P
tot
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
400
2.5
50
3.5
V
A
W
motor
control
purpose
PINNING - TO220AB
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
tab
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DS
Drain-source voltage
V
DGR
Drain-gate voltage
±
V
GS
Gate-source voltage
I
D
Drain current (DC)
CONDITIONS
MIN.
-
-
-
-
-
-
MAX.
400
400
30
2.5
1.6
10
UNIT
V
V
V
A
A
A
R
GS
= 20 k
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
I
DM
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
I
DR
T
mb
= 25 C
-
2.5
A
I
DRM
T
mb
= 25 C
-
10
A
P
tot
T
stg
T
j
T
mb
= 25 C
-
50
150
150
W
C
C
-55
-
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 2.5 A ; V
DD
≤
50 V ; V
GS
= 10 V ;
R
GS
= 50
MIN.
MAX.
UNIT
T
= 25C prior to surge
T
= 100C prior to surge
-
-
-
120
20
3.6
mJ
mJ
mJ
W
DSR
1
Drain-source repetitive
unclamped inductive turn-off
energy
I
D
= 2.5 A ; V
DD
≤
50 V ;
V
GS
= 10 V ; R
GS
= 50
; T
j
≤
150 C
1. Pulse width and frequency limited by T
j(max)
1 2 3
tab
d
g
s
October 1996
1
Rev 1.000