參數(shù)資料
型號: PHB60N06T
廠商: NXP SEMICONDUCTORS
元件分類: JFETs
英文描述: TrenchMOS transistor Standard level FET
中文描述: 58 A, 55 V, 0.02 ohm, N-CHANNEL, Si, POWER, MOSFET
封裝: PLASTIC PACKAGE-3
文件頁數(shù): 1/8頁
文件大小: 68K
代理商: PHB60N06T
Philips Semiconductors
Product specification
TrenchMOS
transistor
Standard level FET
PHB60N06T
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
standard level field-effect power
transistor
in
a
suitable for surface mounting. Using
trench
technology
featuresverylow on-state resistance
and has integral zener diodes giving
ESD protection up to 2kV. It is
intended
for
use
converters and
switching applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
plastic envelope
V
DS
I
D
P
tot
T
j
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Junction temperature
Drain-source on-state
resistance
55
58
150
175
20
V
A
W
C
m
the
device
V
GS
= 10 V
in
DC-DC
general purpose
PINNING - SOT404
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
mb
drain
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL
V
DS
V
DGR
±
V
GS
I
D
I
D
I
DM
P
tot
T
stg
, T
j
PARAMETER
Drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current (DC)
Drain current (DC)
Drain current (pulse peak value)
Total power dissipation
Storage & operating temperature
CONDITIONS
-
R
GS
= 20 k
-
T
mb
= 25 C
T
mb
= 100 C
T
mb
= 25 C
T
mb
= 25 C
-
MIN.
-
-
-
-
-
-
-
- 55
MAX.
55
55
20
58
40
232
150
175
UNIT
V
V
V
A
A
A
W
C
ESD LIMITING VALUE
SYMBOL
V
C
PARAMETER
Electrostatic discharge capacitor
voltage, all pins
CONDITIONS
Human body model
(100 pF, 1.5 k
)
MIN.
-
MAX.
2
UNIT
kV
THERMAL RESISTANCES
SYMBOL
R
th j-mb
PARAMETER
Thermal resistance junction to
mounting base
Thermal resistance junction to
ambient
CONDITIONS
-
TYP.
-
MAX.
1.0
UNIT
K/W
R
th j-a
Minimum footprint, FR4
board
50
-
K/W
d
g
s
1
3
mb
2
December 1997
1
Rev 1.100
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