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參數(shù)資料
| 型號(hào)： | PH8230E |
| 英文描述： | 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to +70°C |
| 中文描述： | TrenchMOS（商標(biāo)）加強(qiáng)場(chǎng)效應(yīng)晶體管邏輯電平 |
| 文件頁(yè)數(shù)： | 5/12頁(yè) |
| 文件大小： | 232K |
| 代理商： | PH8230E |
Philips Semiconductors
PH8230E
TrenchMOS enhanced logic level FET
Product data
Rev. 02 — 29 April 2003
5 of 12
9397 750 11388
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
5.
Characteristics
Table 4:
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
V
GS(th)
gate-source threshold voltage
Characteristics
Conditions
Min
Typ
Max
Unit
I
D
= 250
μ
A; V
GS
= 0 V
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°
C
T
j
= 150
°
C
V
DS
= 30 V; V
GS
= 0 V
T
j
= 25
°
C
T
j
= 150
°
C
V
GS
=
±
20 V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 10 A;
Figure 7
and
8
T
j
= 25
°
C
T
j
= 150
°
C
V
GS
= 4.5 V; I
D
= 10 A;
Figure 7
30
-
-
V
1
0.5
1.7
-
2.5
-
V
V
I
DSS
drain-source leakage current
-
-
-
0.06
-
20
1
500
100
μ
A
μ
A
nA
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
-
-
-
7.6
13
11
8.2
14
13.2
m
m
m
Dynamic characteristics
Q
g(tot)
total gate charge
Q
gs
gate-source charge
Q
gd
gate-drain (Miller) charge
C
iss
input capacitance
C
oss
output capacitance
C
rss
reverse transfer capacitance
t
d(on)
turn-on delay time
t
r
rise time
t
d(off)
turn-off delay time
t
f
fall time
Source-drain diode
V
SD
source-drain (diode forward) voltage I
S
= 10 A; V
GS
= 0 V;
Figure 12
t
rr
reverse recovery time
I
D
= 20 A; V
DD
= 10 V; V
GS
= 5 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
14
5.7
5
1400 -
527
235
28
123
33
21
-
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
GS
= 0 V; V
DS
= 10 V; f = 1 MHz;
Figure 11
-
-
-
-
-
-
V
DD
= 10 V; I
D
= 10 A; V
GS
= 4.5 V; R
G
= 4.7
-
-
0.85
38
1.2
-
V
ns
I
S
= 20 A; dI
S
/dt =
100 A/
μ
s; V
DS
= 20 V
V
GS
= 0 V
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