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    參數(shù)資料
    型號(hào): PH4840S
    廠商: NXP SEMICONDUCTORS
    元件分類: JFETs
    英文描述: N-channel TrenchMOS intermediate level FET
    中文描述: 94.5 A, 40 V, 0.0048 ohm, N-CHANNEL, Si, POWER, MOSFET, MO-235
    封裝: PLASTIC, LFPAK-4
    文件頁數(shù): 5/12頁
    文件大?。?/td> 84K
    代理商: PH4840S
    Philips Semiconductors
    PH4840S
    N-channel TrenchMOS intermediate level FET
    Preliminary data
    Rev. 01 — 04 March 2004
    5 of 12
    9397 750 12814
    Koninklijke Philips Electronics N.V. 2004. All rights reserved.
    6.
    Characteristics
    Table 5:
    T
    j
    = 25
    °
    C unless otherwise specified.
    Symbol Parameter
    Static characteristics
    V
    (BR)DSS
    drain-source breakdown voltage
    V
    GS(th)
    gate-source threshold voltage
    Characteristics
    Conditions
    Min
    Typ
    Max
    Unit
    I
    D
    = 10 mA; V
    GS
    = 0 V
    I
    D
    = 1 mA; V
    DS
    = V
    GS
    ;
    Figure 9
    T
    j
    = 25
    °
    C
    T
    j
    = 150
    °
    C
    V
    DS
    = 40 V; V
    GS
    = 0 V
    T
    j
    = 25
    °
    C
    T
    j
    = 150
    °
    C
    V
    GS
    =
    ±
    20 V; V
    DS
    = 0 V
    V
    GS
    = 10 V; I
    D
    = 25 A;
    Figure 7
    and
    8
    T
    j
    = 25
    °
    C
    T
    j
    = 150
    °
    C
    V
    GS
    = 7 V; I
    D
    = 25 A;
    Figure 7
    and
    8
    40
    -
    -
    V
    1
    0.5
    2
    -
    3
    -
    V
    V
    I
    DSS
    drain-source leakage current
    -
    -
    -
    -
    -
    -
    -
    0.06
    -
    2
    1
    500
    100
    μ
    A
    μ
    A
    nA
    I
    GSS
    R
    DSon
    gate-source leakage current
    drain-source on-state resistance
    3.5
    5.6
    3.85
    4.1
    7.0
    4.8
    m
    m
    m
    Dynamic characteristics
    Q
    g(tot)
    total gate charge
    Q
    gs
    gate-source charge
    Q
    gd
    gate-drain (Miller) charge
    C
    iss
    input capacitance
    C
    oss
    output capacitance
    C
    rss
    reverse transfer capacitance
    t
    d(on)
    turn-on delay time
    t
    r
    rise time
    t
    d(off)
    turn-off delay time
    t
    f
    fall time
    Source-drain diode
    V
    SD
    source-drain (diode forward) voltage I
    S
    = 25 A; V
    GS
    = 0 V;
    Figure 12
    t
    rr
    reverse recovery time
    I
    D
    = 30 A; V
    DD
    = 32 V; V
    GS
    = 10 V;
    Figure 13
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    67
    8.6
    16
    3660
    877
    454
    21
    35
    82
    31
    -
    -
    -
    -
    -
    -
    -
    -
    -
    -
    nC
    nC
    nC
    pF
    pF
    pF
    ns
    ns
    ns
    ns
    V
    GS
    = 0 V; V
    DS
    = 10 V; f = 1 MHz;
    Figure 11
    V
    DD
    = 20 V; I
    D
    = 25 A;
    V
    GS
    = 10 V; R
    G
    = 4.7
    -
    -
    0.85
    46
    1.2
    -
    V
    ns
    I
    S
    = 20 A; dI
    S
    /dt =
    100 A/
    μ
    s; V
    GS
    = 0 V
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