參數(shù)資料
型號(hào)： PF38F40L0YUQ0
廠商： NUMONYX
元件分類(lèi)： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁(yè)數(shù)： 81/99頁(yè)
文件大小： 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18)
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
Datasheet
July 2006
82
Order Number: 313295-002US
Figure 34. Buffered EFP Flowchart
Write Data @ 1ST
Word Address
Last
Data?
Write 0xFFFF,
Address Not within
Current Block
Program
Done?
Read Status Reg.
Y
No (SR[7]=0)
Full Status Check
Procedure
Program
Complete
Read Status Reg.
BEFP
Exited?
Yes (SR[7]=1)
Start
Write 0x80 @
1ST Word Address
V
PP applied,
Block unlocked
Write 0xD0 @
1STWord Address
BEFP Setup
Done?
Read Status Reg.
Exit
N
Program & Verify Phase
Exit Phase
Setup Phase
BUFFERED ENHANCED FACTORY PROGRAMMING (Buffered-EFP) PROCEDURE
X = 32?
Initialize Count:
X = 0
Increment Count:
X = X+1
Y
NOTES:
1. First-word address to be programmed within the target block
must be aligned on a write-buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address;
WSM internally increments addressing.
N
Check V
PP, Lock
Errors (SR[3,1])
Yes (SR[7]=0)
Comments
Bus
State
Operation
BEFP setup delay
Data Stream
Ready?
Read Status Reg.
No (SR[0]=1)
Repeat for subsequent blocks;
After BEFP exit, a full Status Register check can
determine if any program error occurred;
See full Status Register check procedure in the
Word Program flowchart.
Write 0xFF to enter Read Array state.
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
Check Exit
Status
Read
Status
Register
Data = Status Reg. Data
Address = 1ST Word Addr
BEFP Exit
Standby
If SR[7] is set, check:
SR[3] set = V
PP Error
SR[1] set = Locked Block
Error
Condition
Check
Standby
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
BEFP
Setup
Done?
Standby
Data = Status Reg. Data
Address = 1STWord Addr
Status
Register
Read
Data = 0xD0 @
1
ST Word
Address
BEFP
Confirm
Write
Data = 0x80 @ 1ST Word
Address
BEFP
Setup
Write
(Note 1)
V
PPHapplied to VPP
Unlock
Block
Write
BEFP Setup
Bus
State
Comments
Operation
No (SR[0]=1)
Yes (SR[0]=0)
No (SR[7]=1)
Yes (SR[0]=0)
BEFP Program & Verify
Comments
Bus State Operation
Write
(Note 2)
Load
Buffer
Standby
Increment
Count
Standby
Initialize
Count
Data = Data to Program
Address = 1ST Word Addr.
X = X+1
X = 0
Standby
Buffer
Full?
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Read
Standby
Status
Register
Data Stream
Ready?
Data = Status Register Data
Address = 1ST Word Addr.
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Read
Standby
Write
Status
Register
Program
Done?
Last
Data?
Exit Prog &
Verify Phase
Data = Status Reg. data
Address = 1ST Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
No = Fill buffer again
Yes = Exit
Data = 0xFFFF @ address not in
current block
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