參數(shù)資料
型號： PF38F40L0YUQ0
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁數(shù)： 40/99頁
文件大?。?/td> 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
45
Intel StrataFlash Wireless Memory (L18)
“flow through” behavior only applies to the first access of any synchronous read bus
cycle. All subsequent data is driven on valid clock edges following the first access
latency; however, for a synchronous non-array read, the same word of data will be
output on successive clock edges until the burst length requirements are satisfied.
During synchronous read operations, after OE# is driven low WAIT indicates invalid
data on subsequent clock edges when asserted, and valid data when de-asserted with
respect to a valid clock edge. See Figure 7, “Synchronous Array Read with Flow-
for additional details. Synchronous burst reads are permitted in all blocks.
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access
latency incurred when system software needs to suspend a burst sequence that is in
progress in order to retrieve data from another device on the same system bus. The
system processor can resume the burst sequence later. Burst suspend provides
maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained. A
burst sequence can be suspended and resumed without limit as long as device
operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at VIH or VIL.
To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK
edges resume the burst sequence. See Figure 9, “Burst Suspend Timing” on page 29.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 9.2, “Device Commands”
RCR contents can be examined using the Read Device Identifier command, and then
reading from <partition base address> + 0x05 (see Section 15.2, “Read Device
The RCR is shown in Table 15. The following sections describe each RCR bit
.
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