參數(shù)資料
型號(hào)： PF38F40L0YUQ0
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 1.8V PROM, PBGA88
封裝： 8 X 11 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-88
文件頁(yè)數(shù)： 36/99頁(yè)
文件大小： 1419K
代理商： PF38F40L0YUQ0
Intel StrataFlash Wireless Memory (L18) with A/D-Multiplexed I/O
July 2006
Datasheet
Order Number: 313295-002US
41
Intel StrataFlash Wireless Memory (L18)
9.3
Command Definitions
Table 14 shows valid device command codes and descriptions.
Table 13. Command Bus Cycles
Mode
Command
Bus
Cycles
First Bus Cycle
Second Bus Cycle
Note
s
Oper Addr Data Oper Addr
Data
Read
Read Array
1Write
PnA
0xFF
1,2
Read Device Identifier
≥ 2
Write
PnA
0x90
Read
PBA+IA
ID
CFI Query
≥ 2
Write
PnA
0x98
Read
PnA+QA QD
Read Status Register
2
Write
PnA
0x70
Read
PnA
SRD
Clear Status Register
1Write
X
0x50
Program
Word Program
2Write
WA
0x40/
0x10
Write
WA
WD
Buffered Program
> 2
Write
WA
0xE8
Write
WA
N - 1
1,2,3
Buffered Enhanced Factory Program
(Buffered EFP)
> 2
Write
WA
0x80
Write
WA
0xD0
1,2,4
Erase
Block Erase
2
Write
BA
0x20
Write
BA
0xD0
1,2
Suspend
Program/Erase Suspend
1Write
X
0xB0
Program/Erase Resume
1Write
X
0xD0
Block
Locking/
Unlocking
Lock Block
2
Write
BA
0x60
Write
BA
0x01
Unlock Block
2
Write
BA
0x60
Write
BA
0xD0
Lock-down Block
2
Write
BA
0x60
Write
BA
0x2F
Protection
Program Protection Register
2
Write
PRA
0xC0
Write
PRA
PD
Program Lock Register
2
Write
LRA
0xC0
Write
LRA
LRD
Configuration Program Read Configuration Register
2Write
RCD
0x60
Write
RCD
0x03
Notes:
1.
First command cycle address should be the same as the operation’s target address.
PnA = Address within the partition.
PBA = Partition base address.
IA = Identification code address offset.
QA = CFI Query address offset.
BA = Address within the block.
WA = Word address of memory location to be written.
PRA = Protection Register address.
LRA = Lock Register address.
X = Any valid address within the device.
2.
ID = Identifier data.
QD = Query data on AD[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
PD = Protection Register data.
LRD = Lock Register data.
RCD = Read Configuration Register data on A[15:0]. A[MAX:16] can select any partition.
3.
The second cycle of the Write-to-Buffer command is the word count of the data to be loaded into the write buffer. This is
followed by up to 32 words of data.Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4.
The confirm command (0xD0) is followed by the buffer data.
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