參數(shù)資料
型號(hào)： PDI1394P11ABD
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 3-port physical layer interface
中文描述： 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64
封裝： 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64
文件頁(yè)數(shù)： 5/20頁(yè)
文件大小： 135K
代理商： PDI1394P11ABD
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
5
associated link controller. The received data is also transmitted out
the other active cable ports.
The cable status, bus initialization and arbitration states are
monitored through the cable interface using differential comparators.
The outputs of these comparators are used by internal logic to
determine cable and arbitration status. The TPA channel monitors
the incoming cable common-mode voltage value during arbitration to
determine the speed of the next packet transmission. The TPB
channel monitors the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias voltage,
indicating the cable connection status.
The PDI1394P11A provides a nominal 1.85 V for driver load
termination. This bias voltage, when seen through a cable by a
remote receiver, is used to sense the presence of an active
connection. The value of this bias voltage has been chosen to allow
inter-operability between transceiver chips operating from either 5 V
nominal supplies, or 3.3 V nominal supplies. This bias voltage
source should be stabilized by using an external filter capacitor. When
not powered, the PDI1394P11A prevents the bias voltage from
erroneously powering up the part as is seen in some other Phys.
8.0
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITION
LIMITS
UNIT
MIN
TYP
MAX
V
DD
V
IH
V
IL
V
ID–100
V
ID–200
V
ID–ARB
DC supply voltage
Source/non-source power node
2.7
3.3
3.6
V
High level input voltage
CMOS inputs
2.0
5.5
V
Low level input voltage
CMOS inputs
0.8
V
Differential input voltage
Cable inputs, 100Mbit operation
142
260
mV
Differential input voltage
Cable inputs, 200Mbit operation
132
260
mV
Differential input voltage
Cable inputs, during arbitration
171
262
mV
V
IC–100
Common mode voltage
TPB cable inputs, 100Mbit or speed signaling OFF,
source power node
1.165
2.515
V
TPB cable inputs, 100Mbit or speed signaling OFF,
non–source power node
1.165
2.015
V
IC–200SP
Common mode voltage
TPB cable inputs, 200Mbit or speed signaling,
source power node
0.935
2.515
V
TPB cable inputs, 200Mbit or speed signaling,
non–source power node
0.935
2.015
Receive input jitter
TPA, TPB cable inputs, 100Mbit operation
±
1.08
±
0.5
ns
TPA, TPB cable inputs, 200Mbit operation
ns
Receive input skew
Between TPA and TPB cable inputs, 100Mbit
operation
±
0.8
ns
Between TPA and TPB cable inputs, 200Mbit
operation
±
0.55
ns
I
OL
/I
OH
Output current I
Output current, I
OL
/I
OH
SYSCLK
–16
16
mA
Control, Data, CNA, C/LKON
–12
12
I
O
Output current
TPBIAS outputs
–3
1.3
mA
f
XTAL
Crystal frequency
Parallel resonant fundamental mode crystal
24.5735
24.576
24.5785
MHz
T
amb
Operating ambient
temperature range in free air
0
+70
°
C
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參數(shù)描述
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PDI1394P11BD 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface
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