- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382386 > PDI1394P11ABD (NXP SEMICONDUCTORS) 3-port physical layer interface PDF資料下載
參數(shù)資料
| 型號(hào)： | PDI1394P11ABD |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3-port physical layer interface |
| 中文描述： | 3 CHANNEL(S), 200M bps, SERIAL COMM CONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, SOT-314-2, LQFP-64 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 135K |
| 代理商： | PDI1394P11ABD |
Philips Semiconductors
Preliminary specification
PDI1394P11A
3-port physical layer interface
1999 Mar 10
3
5.0
PIN DESCRIPTION
PIN NUMBER
PIN SYMBOL
I/O
NAME AND FUNCTION
1
RESET–
I*
Phy reset, active LOW
2
LPS
I*
Link Layer Controller (LLC) power status
3
LREQ
I*
Link request from controller
4
DVDD
I*
Should be connected to the LLC V
supply when a 5V LLC is connected to the
Phy, and should be connected to the Phy DVDD when a 3V LLC is used.
5, 6, 19, 20
DVDD
D
I
Digital circuit power
7
PD
I*
Device power down input
8, 10, 17, 18, 63, 64
DGND
–
Digital circuit ground
9
SYSCLK
O*
49.152 MHz clock to link controller
11, 12
CTL[0:1]
I/O*
Link interface bi-directional control signals
13, 14, 15, 16
D[0:3]
I/O*
Link interface bi-directional data signals
22, 21
TESTM[1:2]
I*
Test/Mode Control pins
11 =1394–1995 mode
10 = 1394a mode
00/01 = Reserved
23
CPS
I
Cable power status
24, 25, 51, 55
AVDD
–
Analog circuit power
26, 32, 41, 49, 50, 61
AGND
–
Analog circuit ground
27
C/LKON
I/O*
Bus/Isochronous Resource Manager capable input, or LINK-ON signal output
30, 29, 28
PC[0:2]
I*
Power class bits 0 through 2 inputs
31
CNA
O*
Cable Not Active output
36, 40, 45
TPA[1:3]+
I/O
Port n cable pair A, positive signal
35, 39, 44
TPA[1:3]–
I/O
Port n cable pair A, negative signal
34, 38, 43
TPB[1:3]+
I/O
Port n cable pair B, positive signal
33, 37, 42
TPB[1:3]–
I/O
Port n cable pair B, negative signal
46, 47, 48
TPBIAS[1:3]
O
Cable termination voltage supplies
52, 53
PLLGND
–
PLL circuit ground
54
FILTER
I/O
PLL external filter capacitor
56
XI
I
Crystal oscillator connection
57
XO
O
Crystal oscillator connection
58
PLLVDD
–
PLL circuit power
59, 60
R[0:1]
–
External current setting resistor
62
ISO–
I*
Link interface isolation status input
NOTE:
* Indicates 5V tolerant structure.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394P25BY | 1-port 400 Mbps physical layer interface |
| PDI20AC1H0R | |
| PDI20AC1H0X | |
| PDI20AC1HR0 | |
| PDI20AC1HRX | |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394P11ABD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| PDI1394P11BD | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P11BD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Transceiver |
| PDI1394P21 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P21BE | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:3-port physical layer interface |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。