- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382384 > PCM66P 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER PDF資料下載
參數(shù)資料
| 型號(hào)： | PCM66P |
| 英文描述： | 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位CMOS單片音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 7/7頁(yè) |
| 文件大小： | 92K |
| 代理商： | PCM66P |
PCM66P
7
P3 (CLK)
P4 (DATA)
P2 (WDCLK)
P1 (LRCLK)
60ns min
15ns min
15ns min
WDCLK DUTY CYCLE
WDCLK is the input signal that controls when data is loaded
and how long each output is in the integrate mode. It is
therefore recommended that a 50% (high) duty cycle be
maintained on WDCLK. This will ensure that each output
will have enough time to reach its final output value, and that
the output level of each channel will be within the gain
mismatch specification. Refer to Figure 1 for exact timing
relationships of WDCLK to CLK and LRCLK and the
outputs of the PCM66P. The WDCLK can be high longer
than 50%, as long as setup and hold times shown in Figure
5 are observed and the time high is roughly equivalent for
both left and right channels.
SETUP AND HOLD TIME
The individual serial data bit shifts, the serial to parallel data
transfer, and left/right control are triggered on positive CLK
edges. The setup time required for DATA, WDCLK, and
LRCLK to be latched by the next positive going CLK is
15ns minimum. A minimum hold time of 15ns is also
required after the positive going CLK edge for each data bit
to be shifted into the serial input register. Refer to Figure 5
for the timing relationship of these signals.
MAXIMUM CLOCK RATE
The 100% tested maximum clock rate of 8.47MHz for the
PCM66P is derived by multiplying the standard audio sample
rate of 44.1kHz times eight (4
X
oversampling times two
channels) times the standard audio word bit length of 24
(44.1kHz
x
4
x
2
x
24 = 8.47MHz). Note that this clock rate
accommodates a 24-bit word length, even though only 16
bits are actually being used.
“STOPPED-CLOCK” OPERATION
The PCM66P is normally operated with a continuous clock
input signal. If the clock is to be stopped between input data
words, the last 16 bits shifted in are not actually shifted from
the serial register to the latched parallel DAC register until
the first clock after the one used to input bit 16 (LSB). This
means the data is not shifted into the DHC latch until the
start of the next 16-bit data word input, unless at least one
additional clock accompanies the 16 used to serially shift in
data in the first place. In either case, the setup and hold times
for DATA, WDCLK, and LRCLK must still be observed.
INSTALLATION
The PCM66P only requires a single +5V supply. The +5V
supply, however, is used in deriving the internal reference.
It is therefore very important that this supply be as “clean”
as possible to reduce coupling of supply noise to the outputs.
If a good analog supply is available at greater than +5V, a
zener diode can be used to obtain a stable +5V supply. A
FIGURE 5. PCM66P Setup and Hold Timing Diagram.
100
μ
F decoupling capacitor as shown in Figure 3 should be
used regardless of how good the +5V supply is to maximize
power supply rejection. All grounds should be connected to
the analog ground plane as close to the PCM66P as possible.
FILTER CAPACITOR REQUIREMENTS
As shown in Figure 3, C
and V
SENSE should have
decoupling capacitors of 0.1
μ
F (C
) and 10
μ
F (C
) to +V
respectively with no special tolerance being required. To
maximize channel separation between left and right chan-
nels, 5% 300pF capacitors (C
and C
) between V
and left
and right channel outputs are required in addition to a 5%
3
μ
F capacitor (C
) between V
and +5V. The ratio of 10k
to 1 is the important factor here for proper circuit operation.
Placement of all capacitors should be as close to the appro-
priate pins of the PCM66P as possible to reduce noise
pickup from surrounding circuitry.
APPLICATIONS
Probably the most popular use of the PCM66P is in applica-
tions requiring single power supply operation. For example,
the PCM66P is ideal for automotive compact disk (CD) and
digital audio tape (DAT) playback units. To use a more
complex bipolar DAC requiring
±
5V supplies in the +12V
application, for example, would require driving a stable
“floating” ground and regulating the +12V to +10V. The
single supply CMOS PCM66P would only require a +5V
zener diode to regulate its 50mW max supply. The outputs
could be AC coupled to the rest of the circuit for perfectly
acceptable high dynamic performance. The PCM66P is ideal
in any application requiring a minimum of additional cir-
cuitry as well as ultra-low-power CMOS performance.
Of course, the PCM66P is the D/A converter of choice in
any application requiring very low power dissipation. Por-
table battery powered test and measurement equipment re-
quiring very low distortion digital to analog converters
would be an ideal application for the CMOS PCM66P with
its 50mW max power dissipation.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PCO-6130 | PULSED/CW LASER DIODE DRIVER MODULE |
| PCO-7110 | PULSED LASER DIODE DRIVER MODULE |
| PCO24 | PC(ISA)BUS I/O CARD |
| PCT-1611 | Transformer |
| PCT-1616 | Transformer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCM67 | 制造商:BB 制造商全稱:BB 功能描述:Advanced 1-Bit BiCMOS Dual 18-Bit DIGITAL-TO-ANALOG CONVERTER |
| PCM-67 | 功能描述:電線鑒定 Pre-Printed WM Card, Vinyl Cloth, .22" W RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PCM-675-699 | 制造商:Panduit Corp 功能描述:Call vendor for pricing |
| PCM-67-99 | 功能描述:電線鑒定 1.5 VINYL CLTH 67-99 RoHS:否 制造商:TE Connectivity / Q-Cees 產(chǎn)品:Labels and Signs 類型: 材料:Vinyl 顏色:Blue 寬度:0.625 in 長(zhǎng)度:1 in |
| PCM67P | 制造商:BURR-BROWN 功能描述: 制造商:Texas Instruments 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。