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參數(shù)資料
| 型號(hào)： | PCM66P |
| 英文描述： | 16-Bit CMOS Monolithic Audio DIGITAL-TO-ANALOG CONVERTER |
| 中文描述： | 16位CMOS單片音頻數(shù)字模擬轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 92K |
| 代理商： | PCM66P |
6
PCM66P
DIGITAL INPUT
ANALOG OUTPUT
Binary Two’s
Complement (Hex)
Voltage (V)
V
OUT
Mode
DAC Output (V)
7FFF
0000
8000
2E5B
+FS
BPZ
–FS
V
COM
+3.5629443
+2.1629871
+0.7630299
+2.6700000
DISCUSSION OF
SPECIFICATIONS
TOTAL HARMONIC DISTORTION + NOISE
The key specification for the PCM66P is total harmonic
distortion plus noise. Digital data words are read into the
PCM66P at four times the standard audio sampling fre-
quency of 44.1kHz or 176.4kHz for each channel, such that
a sine wave output of 991Hz is realized. For production
testing, the output of the DAC goes to a programmable gain
amplifier to provide gain at lower signal output test levels
and then through a 20kHz low pass filter before being fed
into an analog type distortion analyzer. Figure 4 shows a
block diagram of the production THD + N test setup.
In terms of signal measurement, THD + N is the ratio of
Distortion
+ Noise
/Signal
expressed in dB. For the
PCM66P, THD + N is 100% tested at three different output
levels using the test setup shown in Figure 4. It is significant
to note that this circuit does not include any output deglitching
circuitry. This means the PCM66P meets even its –60dB
THD + N specification without use of external deglitchers.
ABSOLUTE LINEARITY
Even though absolute integral and differential linearity specs
are not given for the PCM66P, the extremely low THD + N
performance is typically indicative of 14-bit to 15-bit inte-
gral linearity in the DAC depending on the grade specified.
The relationship between THD + N and linearity, however,
is not such that an absolute linearity specification for every
individual output code can be guaranteed.
IDLE CHANNEL SNR
Another appropriate spec for a digital audio converter is idle
channel signal-to-noise ratio (idle channel SNR). This is the
ratio of the noise on either DAC output at bipolar zero in
relation to the full scale range of the DAC. The output of the
DAC is band limited from 20Hz to 20kHz and an A-
weighted filter is applied to make this measurement.
OFFSET, GAIN, AND TEMPERATURE DRIFT
The PCM66P is specified for other important parameters
such as channel separation and gain mismatch between
output channels. And although the PCM66P is primarily
meant for use in dynamic applications, typical specs are also
given for more traditional DC parameters such as gain error,
bipolar zero offset error, and temperature gain drift.
TIMING CONSIDERATIONS
The data format of the PCM66P is binary two’s complement
(BTC) with the most significant bit (MSB) being first in the
serial input bit stream. Table II describes the exact input data
to voltage output coding relationship. Any number of bits
can precede the 16 bits to be loaded, as only the last 16 will
be transferred to the parallel DAC register on the first
positive edge of CLK (clock input) after WDCLK (word
clock) has gone low. All inputs to the PCM66P are TTL
level compatible.
FIGURE 4. THD + N Test Setup Diagram.
TABLE II. PCM66P Input/Output Relationships.
Distortion Meter
(Shiba Soku Model
725 or Equivalent)
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Meter Settings
Programmable
Gain Amp
0dB to 60dB
Low-Pass
Filter
(Toko APQ-25
or Equivalent)
DUT
(PCM66P)
(PCM60P/66P)
Parallel-to-Serial
Conversion
Digital Code
(EPROM)
Binary
Counter
Timing
Logic
Clock
Latch Enable
Sampling Rate = 44.1kHz x 4 (176.4kHz)
Output Frequency = 991Hz
LOW-PASS FILTER
CHARACTERISTIC
0
–20
–40
–60
–80
–100
–120
G
Frequency (Hz)
1
10 10 10 10 10
5
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